公开(公告)号：US20230164991A1

公开(公告)日：2023-05-25

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02 ,  H10B43/27 ,  H10B43/30

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/30625 ,  G11C16/0408 ,  G11C16/0466 ,  G11C5/025 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230164985A1

公开(公告)日：2023-05-25

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US20240071430A1

公开(公告)日：2024-02-29

申请号：US17895959

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Mithun Kumar Ramasahayam ,  Tomoko Ogura Iwasaki

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/064 ,  G06F3/0679

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.

公开(公告)号：US11688689B2

公开(公告)日：2023-06-27

申请号：US17313814

申请日：2021-05-06

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Jiewei Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: An electronic device comprises a stack structure comprising tiers of alternating conductive structures and insulative structures, staircase structures within the stack structure and including steps defined by edges of the tiers, contacts on the steps of the staircase structures, support pillars extending vertically through the stack structure, and support structures laterally adjacent to the contacts in a first horizontal direction and extending vertically through the stack structure. The support pillars exhibit a lateral dimension relatively larger than a lateral dimension of the contacts and the support structures. Related methods, memory devices, and systems are also described.

公开(公告)号：US12167579B2

公开(公告)日：2024-12-10

申请号：US17533225

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Tracy D. Evans ,  Gloria Y. Yang ,  Jiewei Chen ,  Jing Zhou

IPC: H05K7/20 ,  G05B15/02

Abstract: Systems associated with device temperature adjustment are described. A device temperature adjustment system can include an electronic device having a temperature sensor integrated therein to detect a temperature of the electronic device and a temperature adjust module coupled to the electronic device to adjust a temperature of the electronic device based on the detected temperature.

公开(公告)号：US20240046989A1

公开(公告)日：2024-02-08

申请号：US17882053

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Shuangqiang Luo ,  Lifang Xu

IPC: G11C16/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers. The lower stack comprises lower channel-material strings extending through the lower first tiers and the lower second tiers. An upper stack is formed directly above the lower stack. The upper stack comprises vertically-alternating different-composition upper first tiers and upper second tiers. The upper stack comprises upper channel-material strings of select-gate transistors. Individual of the upper channel-material strings are directly electrically coupled to individual of the lower channel-material strings. The upper and lower first tiers are conductive at least in a finished-circuitry construction. The upper and lower second tiers are insulative and comprise insulative material. An insulator tier comprising insulator material is directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers. The insulator material is of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230397424A1

公开(公告)日：2023-12-07

申请号：US18324084

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Everett A. McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Christopher R. Ritchie ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Sijia Yu ,  Naiming Liu

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.

公开(公告)号：US20230395149A1

公开(公告)日：2023-12-07

申请号：US17851865

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  David Ross Economy ,  John D. Hopkins ,  Nancy M. Lomeli ,  Jiewei Chen ,  Rita J. Klein ,  Everett A. McTeer ,  Aaron P. Thurber

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230209818A1

公开(公告)日：2023-06-29

申请号：US17674478

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Nancy M. Lomeli

IPC: H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

CPC classification number: H01L27/11519 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

公开(公告)号：US11049768B2

公开(公告)日：2021-06-29

申请号：US16667733

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jiewei Chen ,  Nancy M. Lomeli

IPC: H01L21/4763 ,  H01L21/768 ,  H01L27/11582 ,  G11C5/02 ,  H01L27/11556

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures. Apertures are formed to extend to surfaces of the insulative structures at different depths than one another within the stack structure. Dielectric liner structures are formed within the apertures. Sacrificial structures are formed within portions of the apertures remaining unoccupied by the dielectric liner structures. Upper portions of the sacrificial structures are replaced with capping structures. Portions of the insulative structures and remaining portions of the sacrificial structures are replaced with electrically conductive material. Microelectronic devices and electronic systems are also described.