公开(公告)号：US20220392535A1

公开(公告)日：2022-12-08

申请号：US17336913

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  Yen Chun Lee ,  Jessica Chen ,  Francesco Douglas Verna-Ketel

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08

Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.

公开(公告)号：US11475970B1

公开(公告)日：2022-10-18

申请号：US17337808

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Yen Chun Lee ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C29/12

Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

公开(公告)号：US20220278103A1

公开(公告)日：2022-09-01

申请号：US17745298

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/788 ,  H01L29/24 ,  H01L29/786

Abstract: Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

公开(公告)号：US20220246221A1

公开(公告)日：2022-08-04

申请号：US17167618

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Nevil N. Gajera ,  Karthik Sarpatwari ,  Zhongyuan Lu

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

公开(公告)号：US20220223605A1

公开(公告)日：2022-07-14

申请号：US17712674

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

公开(公告)号：US20220223203A1

公开(公告)日：2022-07-14

申请号：US17711211

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Robert J. Gleixner ,  Karthik Sarpatwari

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.

公开(公告)号：US11367484B1

公开(公告)日：2022-06-21

申请号：US17154644

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Yen Chun Lee ,  Nevil N. Gajera ,  Karthik Sarpatwari

IPC: G11C11/4074 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C13/00

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

公开(公告)号：US20220013183A1

公开(公告)日：2022-01-13

申请号：US16926556

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

公开(公告)号：US10964385B1

公开(公告)日：2021-03-30

申请号：US16684526

申请日：2019-11-14

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Nevil Gajera ,  Karthik Sarpatwari

IPC: G11C7/00 ,  G11C13/00

Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

公开(公告)号：US10943657B1

公开(公告)日：2021-03-09

申请号：US16544669

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Jessica Chen ,  Nevil Gajera

IPC: G11C13/00

Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.