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    Bus Training with Interconnected Dice
    4.
    发明公开
    Bus Training with Interconnected Dice 审中-公开

    公开(公告)号：US20240070101A1

    公开(公告)日：2024-02-29

    申请号：US17823415

    申请日：2022-08-30

    申请人： Micron Technology, Inc.

    发明人： Francesco Douglas Verna-Ketel ,  Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim

    IPC分类号： G06F13/40 ,  G06F13/16

    CPC分类号： G06F13/4027 ,  G06F13/1668

    摘要： Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

    Bus Training with Interconnected Dice
    6.
    发明公开
    Bus Training with Interconnected Dice 审中-公开

    公开(公告)号：US20240070102A1

    公开(公告)日：2024-02-29

    申请号：US17823423

    申请日：2022-08-30

    申请人： Micron Technology, Inc.

    发明人： Yang Lu ,  Creston M. Dupree ,  Smruti Subhash Jhaveri ,  Hyun Yoo Lee ,  John Christopher Sancon ,  Kang-Yong Kim ,  Francesco Douglas Verna-Ketel

    IPC分类号： G06F13/40 ,  G06F13/16

    CPC分类号： G06F13/4027 ,  G06F13/1668

    摘要： Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

    Programming Intermediate State to Store Data in Self-Selecting Memory Cells
    7.
    发明申请
    Programming Intermediate State to Store Data in Self-Selecting Memory Cells 有权

    公开(公告)号：US20220392535A1

    公开(公告)日：2022-12-08

    申请号：US17336913

    申请日：2021-06-02

    申请人： Micron Technology, Inc.

    发明人： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  Yen Chun Lee ,  Jessica Chen ,  Francesco Douglas Verna-Ketel

    IPC分类号： G11C16/10 ,  G11C16/24 ,  G11C16/08

    摘要： Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.