公开(公告)号：US11568952B2

公开(公告)日：2023-01-31

申请号：US17337195

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Xuan-Anh Tran ,  Nevil N. Gajera ,  Karthik Sarpatwari ,  Amitava Majumdar

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00

Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

公开(公告)号：US11894078B2

公开(公告)日：2024-02-06

申请号：US17825941

申请日：2022-05-26

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

公开(公告)号：US20220013183A1

公开(公告)日：2022-01-13

申请号：US16926556

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

公开(公告)号：US20220392560A1

公开(公告)日：2022-12-08

申请号：US17337195

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Xuan-Anh Tran ,  Nevil N. Gajera ,  Karthik Sarpatwari ,  Amitava Majumdar

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

公开(公告)号：US20220284973A1

公开(公告)日：2022-09-08

申请号：US17825941

申请日：2022-05-26

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

公开(公告)号：US11355209B2

公开(公告)日：2022-06-07

申请号：US16926556

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.