公开(公告)号：US20070179756A1

公开(公告)日：2007-08-02

申请号：US11643933

申请日：2006-12-22

申请人： Takayoshi Honda

发明人： Takayoshi Honda

IPC分类号： G06F15/00 ,  G01L23/22 ,  G06F19/00

CPC分类号： G01L23/225

摘要： A knock sensor signal processing apparatus for an engine, which performs a series of A/D conversions of a knock sensor signal during each of successive knock judgement intervals to obtain A/D converted values for use in judging if engine knocking is occurring in a cylinder, derives compensation coefficients during an interval between the end of a knock judgement interval corresponding to a cylinder and the start of deriving knock sensor signal A/D values in a succeeding knock judgement interval for a succeeding cylinder, and applies these coefficients to correct the A/D converted values derived in the second knock judgement interval.

公开(公告)号：US20070170587A1

公开(公告)日：2007-07-26

申请号：US11656431

申请日：2007-01-23

申请人： Takayoshi Honda

发明人： Takayoshi Honda

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/48227 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A ball grid array includes: a semiconductor chip having multiple pads; and an interposer for mounting the semiconductor chip on a first surface. The interposer includes multiple wirings on the first surface and multiple ball terminals on a second surface opposite to the first surface. Each wiring is connected to a corresponding pad of the semiconductor chip, and is electrically connected to a corresponding ball terminal. At least one of ball terminals providing a power supply terminal or a ground terminal provides a common ball terminal for connecting to at least two of the pads of the semiconductor chip through two wirings.

摘要翻译： 球栅阵列包括：具有多个焊盘的半导体芯片; 以及用于将半导体芯片安装在第一表面上的插入器。 插入器包括第一表面上的多个布线和与第一表面相对的第二表面上的多个球形端子。 每个布线连接到半导体芯片的相应的焊盘，并且电连接到相应的球端子。 提供电源端子或接地端子的球端子中的至少一个提供了通过两条布线连接到半导体芯片的至少两个焊盘的公共球形端子。

公开(公告)号：US07210055B2

公开(公告)日：2007-04-24

申请号：US10283333

申请日：2002-10-30

申请人： Takayoshi Honda

发明人： Takayoshi Honda

IPC分类号： G06F1/04

CPC分类号： F02D41/221 ,  B60W2050/0005 ,  B60W2050/041 ,  F02D41/003 ,  F02D41/2403 ,  F02D2041/2027 ,  F02D2200/503 ,  F02D2400/14

摘要： In an in-vehicle electronic control apparatus (ECU), when a microcomputer stops operation, a timer IC starts the count-up operation. When the count value reaches a preset value, a signal from the timer IC becomes high and a power supply voltage is outputted from a power supply IC to activate the microcomputer. The microcomputer reads the count value from the timer IC when it starts the operation. If such a count value has exceeded the specified value, the microcomputer determines occurrence of a failure. Therefore, if the timer IC cannot activate the power supply IC, the microcomputer can detect a failure upon activation with turning on of an ignition switch.

摘要翻译： 在车载电子控制装置（ECU）中，当微型计算机停止动作时，定时器IC开始向上计数。 当计数值达到预设值时，来自定时器IC的信号变高，并且从电源IC输出电源电压以启动微型计算机。 微型计算机从开始运行时读取定时器IC的计数值。 如果这样的计数值超过规定值，则微机判定故障的发生。 因此，如果定时器IC不能激活电源IC，则微计算机能够通过点火开关的接通来检测激活时的故障。

公开(公告)号：US07003382B2

公开(公告)日：2006-02-21

申请号：US10816936

申请日：2004-04-05

申请人： Takayoshi Honda

发明人： Takayoshi Honda

IPC分类号： G06F12/16

CPC分类号： B60W50/00 ,  B60W50/0098

摘要： In an electronic control unit for a vehicle, control data is stored in a volatile memory until a predetermined time passes after an ignition switch is turned off. This makes it possible to greatly reduce the frequency at which data is written into a nonvolatile memory. When the predetermined time has passed after the ignition switch is turned off, the control data stored in the volatile memory is written into the nonvolatile memory. Thereafter, the power supply from a power supply circuit to the volatile memory is stopped. Consequently, it is possible to store the control data reliably in either the volatile memory or the nonvolatile memory. It is also possible to reduce the dark current in the volatile memory.

摘要翻译： 在用于车辆的电子控制单元中，控制数据被存储在易失性存储器中，直到点火开关关闭之后经过预定时间。 这使得可以大大降低将数据写入非易失性存储器的频率。 当在点火开关关闭之后经过预定时间时，将存储在易失性存储器中的控制数据写入非易失性存储器。 此后，停止从电源电路向易失性存储器的供电。 因此，可以将控制数据可靠地存储在易失性存储器或非易失性存储器中。 还可以减少易失性存储器中的暗电流。

公开(公告)号：US20050136629A1

公开(公告)日：2005-06-23

申请号：US10974970

申请日：2004-10-28

申请人： Katsuhiko Iizuka ,  Kazuo Okada ,  Tomonori Mori ,  Hiroyuki Dobashi ,  Hiroyuki Suzuki ,  Takayoshi Honda ,  Toshimitsu Taniguchi

发明人： Katsuhiko Iizuka ,  Kazuo Okada ,  Tomonori Mori ,  Hiroyuki Dobashi ,  Hiroyuki Suzuki ,  Takayoshi Honda ,  Toshimitsu Taniguchi

IPC分类号： H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/7833

摘要： An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.

摘要翻译： 形成LDD结构和硅化物层，而不会减小硅衬底的厚度或碳污染。 在栅电极的侧壁上形成间隔物，在两个工艺步骤中进行，即干蚀刻和湿蚀刻。 此外，通过湿蚀刻除去用作注入大量杂质的缓冲膜的氮化硅膜。 结果，可以防止硅衬底的厚度减少和碳污染。 此外，由于湿蚀刻可用的高选择比，可以抑制高和低杂质浓度区域和硅化物形成区域在晶片上的位置的深度变化。

公开(公告)号：US20050096865A1

公开(公告)日：2005-05-05

申请号：US10975477

申请日：2004-10-29

申请人： Junji Sugiura ,  Soichiro Arai ,  Takayoshi Honda

发明人： Junji Sugiura ,  Soichiro Arai ,  Takayoshi Honda

IPC分类号： F02D45/00 ,  F02D41/26 ,  F02D41/34 ,  G01D5/245 ,  G01C17/00

CPC分类号： F02D41/009 ,  F02D41/263 ,  F02D2041/0092 ,  G01D5/2457

摘要： An apparatus aims at detecting an angle of a rotating shaft as a train of bits. A first signal including a train of pulses corresponding to angle intervals of a rotation of the rotating shaft is inputted to the apparatus, and a second signal including a train of clock pulses whose clock cycle is a positive integer submultiple of a pulse cycle of the first signal is inputted to the apparatus. In the apparatus, a first counter is indicative of a higher-order of the train of bits, and counts up or down in synchronization with the pulse cycle of the first signal. A second counter is indicative of a lower-order of the train of bits, and counts either up or down in synchronization with the clock cycle of the second signal. The second counter is cleared in synchronization with the pulse cycle of the first signal.

摘要翻译： 一种装置旨在将旋转轴的角度作为比特串来检测。 包括对应于旋转轴的旋转角度间隔的脉冲序列的第一信号被输入到该装置，以及第二信号，其包括一系列时钟脉冲，其时钟周期是第一个脉冲周期的正整数 信号被输入到设备。 在该装置中，第一计数器指示比特序列的高阶，并且与第一信号的脉冲周期同步地向上或向下计数。 第二计数器指示比特序列的低阶，并且与第二信号的时钟周期同步地向上或向下计数。 第二个计数器与第一个信号的脉冲周期同步清零。

公开(公告)号：US06246952B1

公开(公告)日：2001-06-12

申请号：US09259265

申请日：1999-03-01

申请人： Takayoshi Honda

发明人： Takayoshi Honda

IPC分类号： G06F1900

CPC分类号： G01L23/225 ,  F02P5/152 ,  F02P2017/128 ,  G01L23/221 ,  Y02T10/46

摘要： Only predetermined frequency components included in an ion current flowing between an ignition plug and the ground are extracted from the ion current by means of a low pass filter and a high pass filter as a knock detection signal, that is, a signal used for knock detection. This knock detection signal is then subjected to A/D-conversion in an A/D-converter to generate A/D-converted values which are subsequently supplied to a processing unit employed in a digital signal processor. In the processing unit, the A/D-converted values are subjected to a discrete Fourier transform (DFT) frequency analysis. Knock determination based on data obtained from the DFT frequency analysis results in information indicating the operating state of the internal combustion engine. That is, in the frequency analysis of the A/D-converted values obtained as a result of the A/D-conversion of predetermined frequency components of the ion current, a peculiarity such as the occurrence of a knock or the superposition of noise on the signal is clearly recognized.

摘要翻译： 只有通过低通滤波器和高通滤波器从离子电流中提取在火花塞和地面之间流动的离子电流中包含的预定频率分量作为爆震检测信号，即用于爆震检测的信号 。 然后在A / D转换器中对该爆震检测信号进行A / D转换，以产生随后提供给数字信号处理器中使用的处理单元的A / D转换值。 在处理单元中，对A / D转换值进行离散付里叶变换（DFT）频率分析。 基于从DFT频率分析获得的数据的敲击确定导致指示内燃机的运行状态的信息。 也就是说，在作为离子电流的预定频率分量的A / D转换的结果获得的A / D转换值的频率分析中，诸如发生爆震或噪声叠加的特性 信号被清楚地识别。

公开(公告)号：US5916296A

公开(公告)日：1999-06-29

申请号：US659496

申请日：1996-06-05

申请人： Takayoshi Honda

发明人： Takayoshi Honda

IPC分类号： F02D41/26 ,  F02D41/00

CPC分类号： F02D41/266

摘要： To execute high-accuracy control employing communication data of a microprocessor while attempting standardization of the microprocessor, a host microprocessor is provided with a ROM, RAM, CPU, and DMA controller, and a KCS microprocessor is provided with a ROM, RAM, CPU, and DMA controller. The host microprocessor and the KCS microprocessor are connected by a bidirectional communication line. At a predetermined cycle, the CPU of the host microprocessor sends data in the ROM relating to the content of control of the KCS microprocessor to the RAM of the KCS microprocessor. Engine information (A/D values and so on) are sent from the KCS microprocessor to the host microprocessor at a cycle of 4 ms, but sending of ROM data from the host microprocessor to the KCS microprocessor is performed during free time in this sending cycle. The ROM data is divided into a plurality of blocks, and the data is sent block by block.

摘要翻译： 为了在尝试微处理器的标准化的同时执行采用微处理器的通信数据的高精度控制，主微处理器设置有ROM，RAM，CPU和DMA控制器，并且KCS微处理器设置有ROM，RAM，CPU， 和DMA控制器。 主机微处理器和KCS微处理器通过双向通信线连接。 在预定的周期，主微处理器的CPU将与KCS微处理器的控制内容相关的ROM中的数据发送到KCS微处理器的RAM。 发动机信息（A / D值等）以4 ms的周期从KCS微处理器发送到主机微处理器，但是在该发送周期的空闲时间内，从主机微处理器发送ROM数据到KCS微处理器 。 ROM数据被分成多个块，并且数据被逐块发送。

公开(公告)号：US10018390B2

公开(公告)日：2018-07-10

申请号：US14439341

申请日：2012-11-30

申请人： Daisuke Shimamoto ,  Yuji Motomura ,  Osamu Morimoto ,  Takayoshi Honda ,  Tatsuo Ono ,  Koji Nishioka

发明人： Daisuke Shimamoto ,  Yuji Motomura ,  Osamu Morimoto ,  Takayoshi Honda ,  Tatsuo Ono ,  Koji Nishioka

IPC分类号： F25D17/02 ,  F25B49/02 ,  F25B13/00 ,  F25B25/00 ,  F25B31/02 ,  F24F3/06

CPC分类号： F25B49/02 ,  F24F3/065 ,  F25B13/00 ,  F25B25/005 ,  F25B31/02 ,  F25B2313/006 ,  F25B2313/023 ,  F25B2313/0231 ,  F25B2313/0272 ,  F25B2313/02743 ,  F25B2600/13 ,  F25B2600/23 ,  F25B2600/2513 ,  F25B2600/2515 ,  F25B2700/1931 ,  F25B2700/1933 ,  Y02B30/745

摘要： An air-conditioning apparatus includes actuation control means including an actuation unit that sequentially opens heat medium flow switching devices or heat medium flow control devices on a one-by-one basis. The actuation control means performs control in such a manner that start time of driving of pumps is later than start of actuation of the heat medium flow switching devices and the heat medium flow control devices.

公开(公告)号：US09829224B2

公开(公告)日：2017-11-28

申请号：US14342083

申请日：2011-12-16

申请人： Osamu Morimoto ,  Daisuke Shimamoto ,  Koji Azuma ,  Takayoshi Honda

发明人： Osamu Morimoto ,  Daisuke Shimamoto ,  Koji Azuma ,  Takayoshi Honda

IPC分类号： F25B29/00 ,  F25B13/00 ,  F24F11/00 ,  F25B25/00

CPC分类号： F25B29/003 ,  F24F11/42 ,  F24F2110/12 ,  F25B13/00 ,  F25B25/005 ,  F25B2313/006 ,  F25B2313/0231 ,  F25B2339/047 ,  F25B2600/13 ,  Y02B30/745

摘要： A refrigerant circuit is configured by connecting, by pipes, a compressor that compresses a heat-source-side refrigerant, a first refrigerant flow switching device, a heat-source-side heat exchanger, an expansion device, and one or more intermediate heat exchangers that exchange heat between a heat-source-side refrigerant and a heat medium that is different from the heat-source-side refrigerant. A controller performs control of pumps to drive the pumps at a specific pump capacity or higher to circulate the heat medium at a time when a heat recovery defrosting operation for causing the heat-source-side refrigerant that has been heated by the heat medium in the intermediate heat exchangers to flow into the heat-source-side heat exchanger for defrosting purposes.