公开(公告)号：US06188114B1

公开(公告)日：2001-02-13

申请号：US09204016

申请日：1998-12-01

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31119

CPC分类号： H01L29/41783 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/6659

摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。

公开(公告)号：US6166354A

公开(公告)日：2000-12-26

申请号：US876381

申请日：1997-06-16

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： C30B31/12 ,  C30B31/18 ,  F27B5/14

CPC分类号： C30B31/18 ,  C30B31/12

摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.

摘要翻译： 在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。 在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。 监测表面光电压测量，检测退火时间，并控制所选择的过退火。 执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。 在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。 检测点也用于终止退火过程以最小化Dt。

公开(公告)号：US6146978A

公开(公告)日：2000-11-14

申请号：US73639

申请日：1998-05-06

申请人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/44 ,  H01L21/4763 ,  H01L31/119

CPC分类号： H01L21/823871 ,  H01L21/76802 ,  H01L21/76895

摘要： An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

摘要翻译： 在通过隔离层打开的窗口中并通过蚀刻屏障形成层间互连，以露出电极表面和相邻隔离屏障。 层间互连可以布置在底层电极的基本上全部的一部分上，例如绝缘栅场效应晶体管（IGFET）源/漏区表面。 蚀刻屏障提供受控的蚀刻，以允许层间互连重叠在隔离屏障上，而不增加寄生电容，相对于传统的接触不对准。 此外，消除重叠的关注允许通过层间互连增加源/漏区表面积的利用。 此外，蚀刻屏障允许层间互连以多个电路器件的带状电极同时显示标称的任何衬底以互连互连漏电流。

公开(公告)号：US6096639A

公开(公告)日：2000-08-01

申请号：US056835

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76895

摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

摘要翻译： 通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。 在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。 在一些实施例中，钛是用于形成局部互连的合适金属。 用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。 硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。 在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。 在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。

公开(公告)号：US6087706A

公开(公告)日：2000-07-11

申请号：US56834

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/00 ,  H01L29/94

CPC分类号： H01L21/26586 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.

摘要翻译： 描述了一种形成在由浅沟槽隔离区域的侧壁限定的有源区域内的晶体管的半导体集成电路及其制造方法。 在有源区域的一部分上形成栅电极，形成与栅极电极和沟槽侧壁自对准的LDD区域。 形成在栅电极附近并延伸到沟槽侧壁的电介质垫片。 以这种方式，间隔件基本上覆盖LDD区域。 形成与沟槽侧壁相邻的源极区和漏极区，其中间隔物用于保护LDD区的至少一部分以保持S / D区与栅电极边缘的间隔。 以这种方式，维持由LDD区域提供的有利的降低的EM。 在本发明的一些实施例中，通过在沟槽侧壁上注入形成S / D区域。

公开(公告)号：US5885887A

公开(公告)日：1999-03-23

申请号：US847752

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/38

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823842 ,  H01L29/42376

摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.

摘要翻译： 公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层 所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平 在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极 地区。 有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

公开(公告)号：US08528100B2

公开(公告)日：2013-09-03

申请号：US13235353

申请日：2011-09-17

申请人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore ,  Clinton W. Wright

发明人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore ,  Clinton W. Wright

IPC分类号： H04L29/06 ,  G06F21/00

CPC分类号： G06F21/105 ,  G06F9/5061

摘要： A method, system, and computer program product for managing software program installations in a cloud computing environment. An example method includes calculating, by a computer processor, a maximum number of software licenses that could be required according to a software license rule from a software license agreement to run a set of software program instances on a set of servers configured as a computing cloud. Each software program instance is an installation of the software program on a different logical partition, and at least two of the servers from the set of servers are capable of requiring a different number of software licenses according to the software license rule. The method also includes determining if the maximum number of software licenses exceeds an allowed number of software licenses granted in the software license agreement.

摘要翻译： 一种用于管理云计算环境中的软件程序安装的方法，系统和计算机程序产品。 一个示例性方法包括由计算机处理器根据软件许可证规则从软件许可协议计算出可能需要的最大数量的软件许可证，以在配置为计算云的一组服务器上运行一组软件程序实例 。 每个软件程序实例是将软件程序安装在不同的逻辑分区上，并且来自该组服务器的至少两个服务器能够根据软件许可证规则要求不同数量的软件许可证。 该方法还包括确定软件许可证的最大数量是否超过在软件许可协议中授予的允许的软件许可数量。

公开(公告)号：US20130054492A1

公开(公告)日：2013-02-28

申请号：US13222349

申请日：2011-08-31

申请人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore ,  Clinton W. Wright

发明人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore ,  Clinton W. Wright

IPC分类号： G06Q40/00 ,  G06F21/22

CPC分类号： G06Q10/063

摘要： Embodiments include a computer system, method and program product for managing a software program installed on a computer hardware system, the software program subject to a software license. A retrieval of data is performed in which the data indicates actual usage of the software program and the computer hardware system, and processor power of the computer hardware system. In addition, a retrieval of licensing data from the software license is performed in which the licensing data indicates a permitted number of or fee for installations of the software program and a permitted amount of or fee for processor power of the computer hardware system in which the software program is installed. Whether to decommission a copy of the software program based on the data indicating actual usage, the licensing data, a projected amount of future usage of the software program, and criticality of the software program is determined and reported.

摘要翻译： 实施例包括用于管理安装在计算机硬件系统上的软件程序的计算机系统，方法和程序产品，该软件程序受软件许可证管理。 执行数据的检索，其中数据指示软件程序和计算机硬件系统的实际使用以及计算机硬件系统的处理器能力。 此外，执行从软件许可证检索许可数据，其中许可数据指示软件程序的安装的允许数量或费用，以及计算机硬件系统的处理器功率的允许量或费用，其中 软件程序已安装。 是否根据指示实际使用的数据停止软件程序的副本，确定并报告许可数据，软件程序的预计未来使用量以及软件程序的关键性。

公开(公告)号：US06520993B2

公开(公告)日：2003-02-18

申请号：US09753233

申请日：2000-12-29

申请人： Stephen B. James ,  Billy G. Anderson ,  John D. Malone ,  Bradley T. Moore ,  Ronald J. Naughton

发明人： Stephen B. James ,  Billy G. Anderson ,  John D. Malone ,  Bradley T. Moore ,  Ronald J. Naughton

IPC分类号： A61F244

CPC分类号： A61F2/4465 ,  A61F2/28 ,  A61F2/30965 ,  A61F2/442 ,  A61F2/447 ,  A61F2/4611 ,  A61F2002/2817 ,  A61F2002/30112 ,  A61F2002/302 ,  A61F2002/3023 ,  A61F2002/30772 ,  A61F2002/30843 ,  A61F2002/30892 ,  A61F2002/4475 ,  A61F2230/0004 ,  A61F2230/0065 ,  A61F2230/0069 ,  A61F2310/00011 ,  A61F2310/00359

摘要： An implantable spinal graft includes a substantially annular body with opposed superior and inferior surfaces. At least a portion of the superior and inferior surfaces includes a plurality of bone-engaging protrusions. Both of the superior and inferior surfaces also include at least one region that is free of protrusions. Preferably, the protrusion-free regions are centrally disposed and are oriented so as to be parallel to or angled with respect to an anterior-posterior axis of the implant. The implant further includes a tip on the posterior that is formed by converging portion of the superior and inferior surfaces.

公开(公告)号：US6111260A

公开(公告)日：2000-08-29

申请号：US872258

申请日：1997-06-10

申请人： Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01J37/317

CPC分类号： H01J37/3171 ,  H01J2237/316

摘要： During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element. An ion implant device including a system for applying and controlling thermal energy applied to a semiconductor substrate wafer during ion implantation raises the temperature of the wafer to a temperature that is sufficient to activate impurities within the semiconductor substrate wafer when an ion beam is implanting ions to the wafer, but the temperature is insufficient to activate impurities when the ion beam is inactive.

摘要翻译： 在半导体衬底离子注入过程中，提供热能以提高半导体晶片的温度。 在注入期间半导体晶片的温度升高期间用于退火晶片中注入的杂质或掺杂剂，减少杂质扩散并减少制造工艺步骤的数量。 离子注入装置包括终端站，其适于向端站施加和控制热能，以在植入期间提高半导体衬底晶片的温度。 适用的端站包括用于加热半导体衬底晶片的加热元件，用于感测半导体衬底晶片的温度的热电偶，以及用于监测感测温度并通过加热元件控制施加到半导体衬底晶片的热能的控制器 。 包括用于在离子注入期间施加和控制施加到半导体衬底晶片的热能的系统的离子注入装置将晶片的温度升高到当离子束注入离子时足以激活半导体衬底晶片内的杂质的温度 晶片，但当离子束无效时，温度不足以激活杂质。