公开(公告)号：US07403446B1

公开(公告)日：2008-07-22

申请号：US11237378

申请日：2005-09-27

Applicant: Suresh Parameswaran ,  Thinh Tran ,  Joseph Tzou

Inventor： Suresh Parameswaran ,  Thinh Tran ,  Joseph Tzou

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C11/419 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C8/18

Abstract: Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally.

Abstract translation: 同步SRAM可以符合标准 在外部接口同步或提前写入，同时在内部提供后期写入。

公开(公告)号：US07269772B1

公开(公告)日：2007-09-11

申请号：US10785826

申请日：2004-02-23

Applicant: Jun Li ,  Joseph Tzou ,  Thinh Tran

Inventor： Jun Li ,  Joseph Tzou ,  Thinh Tran

IPC: G01R31/28

CPC classification number: G01R31/3187 ,  G01R31/31725

Abstract: An integrated circuit device (200) can include a main portion (204) and a built-in self-test (BIST) portion (204) having outputs coupled to physical input structures (e.g., bond pads) (206) of the integrated circuit device (200). A BIST portion (202) can test timing critical parameters that take into account the effect of input structures (206). A BIST portion (202) can apply BIST test signals with a pipeline structure that can emulate timing parameters, such as a set-up time (Ts) and a clock-to-output time (Tco).

Abstract translation: 集成电路装置（200）可以包括主要部分（204）和内置自检（BIST）部分（204），其具有耦合到集成电路的物理输入结构（例如，接合焊盘）（206）的输出 装置（200）。 BIST部分（202）可以测试考虑到输入结构（206）的影响的时序关键参数。 BIST部分（202）可以应用具有可以模拟定时参数（诸如建立时间（Ts））和时钟到输出时间（Tco）的流水线结构的BIST测试信号。

公开(公告)号：US20220057915A1

公开(公告)日：2022-02-24

申请号：US17404801

申请日：2021-08-17

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F3/0481 ,  G06F3/0485 ,  G06F21/44

Abstract: An orthogonal or multi-dimensional fabric user interface is described herein. A remote server executes an operating system that provides a multi-dimensional fabric for storing content for a particular user. The user can access select content by manipulating the multi-dimensional fabric through a graphical user interface displayed on a display device. In this way, the user experiences and manipulates various data dimensions around the specific content they are accessing, rather than selecting a particular file structure location.

公开(公告)号：US08464145B2

公开(公告)日：2013-06-11

申请号：US12838035

申请日：2010-07-16

Applicant: Edward L. Grivna ,  Gabriel Li ,  Thinh Tran

Inventor： Edward L. Grivna ,  Gabriel Li ,  Thinh Tran

IPC: G06F11/00 ,  H03M13/00

CPC classification number: G06F13/4291 ,  G06F11/1016

Abstract: A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.

Abstract translation: 串行接口设备包括多个串行链路连接，其至少在不同的串行链路连接上接收地址值和至少一个错误检测码（EDC），从至少地址值生成的EDC，地址值的串行链路连接以及 EDC彼此分开操作; 和多个输出串行链路，输出串行链路中的至少第一个输出从对应于地址值的存储器位置读取的数据值，以及至少第二个输出串行链路，与第一个输出串行链路不同，并且与第一个串行链路分开运行 为从内存位置读取的数据值生成的EDC值。

公开(公告)号：US08149643B2

公开(公告)日：2012-04-03

申请号：US12288984

申请日：2008-10-23

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.

Abstract translation: 存储器件和方法可以包括将交替的读和写访问分离到存储器件的不同组。

公开(公告)号：US08095747B2

公开(公告)日：2012-01-10

申请号：US12239532

申请日：2008-09-26

Applicant: Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

Inventor： Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Abstract translation: 在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控​​制器。 配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。 配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

公开(公告)号：US20100103762A1

公开(公告)日：2010-04-29

申请号：US12288984

申请日：2008-10-23

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.

Abstract translation: 存储器件和方法可以包括将交替的读和写访问分离到存储器件的不同组。

公开(公告)号：US20100082861A1

公开(公告)日：2010-04-01

申请号：US12239532

申请日：2008-09-26

Applicant: Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

Inventor： Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F13/28

Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Abstract translation: 在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控​​制器。 配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。 配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

公开(公告)号：US20200371654A1

公开(公告)日：2020-11-26

申请号：US16988413

申请日：2020-08-07

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F3/0485 ,  G06Q50/00 ,  G06F40/106 ,  G06F16/9537

Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

公开(公告)号：US20120014202A1

公开(公告)日：2012-01-19

申请号：US13245856

申请日：2011-09-26

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period

Abstract translation: 在相同时间段中多次访问存储器件的方法可以包括在第一次访问顺序中，与第一时钟周期的第一部分同步地开始对多个存储体之一的访问操作，并开始访问 与第一时钟周期的第二部分同步地操作到多个存储体中的另一个存储体，每个存储体具有单独的访问电路; 并且连续访问之间的时间比对于相同银行的背对背访问的访问速度更快; 其中在访问操作期间，在相同的时间段内访问每个存储体的存储位置