公开(公告)号：US20200168725A1

公开(公告)日：2020-05-28

申请号：US16681640

申请日：2019-11-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Koshi HIMEDA ,  Kazuya KOBAYASHI

IPC: H01L29/73 ,  H01L29/732 ,  H01L29/417 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.

公开(公告)号：US20250167676A1

公开(公告)日：2025-05-22

申请号：US19027470

申请日：2025-01-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koshi HIMEDA ,  Kazuki ITOYAMA ,  Kenji NISHIYAMA ,  Akitomo TAKAHASHI ,  Nobuyoshi ADACHI

IPC: H02M3/00 ,  H02M1/44

Abstract: A DCDC converter module is provided that includes an insulating substrate having first and second surfaces; and a circuit section at the insulating substrate. The circuit section includes a switching element and an output filter connected to the switching element in series from an input end to an output. The output filter has an output inductor, and first and second output capacitors connected in parallel to each other and having different capacitance. A current path from the switching element to the output end of the circuit section penetrates through the insulating substrate from the first surface to the second surface. The first and second output capacitors are different from each other in position in a thickness direction and are arranged to the current path. An inductor component is between a plus terminal of the first output capacitor and a plus terminal of the second output capacitor.

公开(公告)号：US20240420899A1

公开(公告)日：2024-12-19

申请号：US18820634

申请日：2024-08-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tomoyuki ASHIMINE ,  Satoshi SHINDO ,  Koshi HIMEDA

IPC: H01G9/10 ,  H01G9/012 ,  H01G9/025

Abstract: An electronic component that includes: a sealing body having a first plate, a cover part spaced form the first plate, and a sealing metal layer; a functional part spaced from the first plate and in an airtight internal space of the sealing body; a filling resin part filling a space between the sealing body and the functional part; and a via conductor in a first through hole extending through the first plate and in a second through hole extending through the filling resin part and communicating with the first through hole, the via conductor being electrically connected to a pair of electrodes of the functional part. A water vapor transmission rate of the cover part is less than or equal to one-tenth of a water vapor transmission rate of the filling resin part having the same film thickness, or the cover part is made of glass or metal.

公开(公告)号：US20220181470A1

公开(公告)日：2022-06-09

申请号：US17545973

申请日：2021-12-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari SAJI ,  Atsushi KUROKAWA ,  Koshi HIMEDA

IPC: H01L29/737 ,  H01L23/00 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.

公开(公告)号：US20220157930A1

公开(公告)日：2022-05-19

申请号：US17527129

申请日：2021-11-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hisaki KITAGAWA ,  Koshi HIMEDA ,  Jyou KIKURA

IPC: H01L49/02 ,  H01L27/01

Abstract: A passive component includes a substrate having insulating properties and having a surface having a recess, a bottom electrode filling at least a portion of the recess, a dielectric film provided on a surface of the bottom electrode, and a top electrode opposite to the bottom electrode with the dielectric film interposed therebetween. In a height direction perpendicular to the surface of the substrate, a dimension of the bottom electrode is larger than a dimension of the dielectric film.

公开(公告)号：US20210242836A1

公开(公告)日：2021-08-05

申请号：US17167406

申请日：2021-02-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideyuki SATO ,  Koshi HIMEDA

IPC: H03F1/08 ,  H03F3/213 ,  H01L27/102 ,  H01L29/737 ,  H01L23/00

Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.

公开(公告)号：US20200321289A1

公开(公告)日：2020-10-08

申请号：US16838977

申请日：2020-04-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yusuke TANAKA ,  Fumio HARIMA ,  Masayuki AOIKE ,  Koshi HIMEDA

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/66

Abstract: A semiconductor chip includes a compound semiconductor substrate having a pair of main surfaces and a side surface therebetween, a circuit on one main surface of the pair of main surfaces, and first metals on the main surface. The first metals are positioned, in plan view of the main surface, closer to an outer edge of the main surface than the circuit, substantially in a ring shape to surround the circuit with gaps between first metals adjacent to each other. The semiconductor chip further includes second metals on the main surface. The second metals are positioned, in plan view of the main surface, between the circuit and the first metals or closer to the outer edge than the first metals. Also, the second metals each are positioned, in plan view of the side surface, such that at least a part thereof overlaps a gap between the first metals.

公开(公告)号：US20250166931A1

公开(公告)日：2025-05-22

申请号：US19007888

申请日：2025-01-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takeshi FURUKAWA ,  Koshi HIMEDA ,  Shuhei YAMADA

IPC: H01G9/26 ,  H01G9/15

Abstract: A capacitor array that includes: a plurality of capacitor units, where an actual overall capacitance corresponding to an electrostatic capacity for a total area of the capacitor units in an electrostatic capacity of an entirety of the capacitor array is larger than virtual overall capacitance obtained by multiplying a total number n of virtual units corresponding to an inter-center distance p between a first through-conductor and a second through-conductor when the electrostatic capacity Cunit per unit reaches a maximum value by the maximum value of the electrostatic capacity Cunit per unit.

公开(公告)号：US20240380324A1

公开(公告)日：2024-11-14

申请号：US18779985

申请日：2024-07-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshimitsu USHIMI ,  Koshi HIMEDA ,  Nobuyoshi ADACHI ,  Kenji NISHIYAMA

IPC: H02M3/158

Abstract: A voltage converter is provided that includes a variable inductor device that is disposed between an input line and an output line, a switching device that is disposed between the input line and the variable inductor device, a capacitor that is disposed between the output line and a ground line and a control circuit configured to switch an inductance value of the variable inductor device and to switch a control mode of the switching device according to a load current in the output line. The control circuit is configured to set the inductance value of the variable inductor device to a first value when the load current is less than a threshold value and set the inductance value of the variable inductor device to a second value that is smaller than the first value when the load current is higher than the threshold value.

公开(公告)号：US20240355537A1

公开(公告)日：2024-10-24

申请号：US18758276

申请日：2024-06-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshimitsu USHIMI ,  Koshi HIMEDA ,  Kenji NISHIYAMA ,  Hidehiko SASAKI ,  Nobuyoshi ADACHI

IPC: H01F27/29 ,  H01F17/00 ,  H01F27/32

CPC classification number: H01F27/292 ,  H01F17/0013 ,  H01F27/324 ,  H01F2017/0073

Abstract: An inductor component includes an element body having a magnetic material, and a coil that is disposed inside the element body. The coil includes a coil wire that is spirally wound along an axis with a first end of the coil wire at a positive side of the axis and a second end of the coil wire at a negative side of the axis. At least one of a first end surface of the first end of the coil wire and a second end surface of the second end of the coil wire includes a recess, and a portion of the element body is located inside the recess.