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公开(公告)号：US20180342992A1
公开(公告)日：2018-11-29
申请号：US15967914
申请日：2018-05-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideyuki SATO
CPC classification number: H03F3/213 , H03F1/083 , H03F1/302 , H03F3/195 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/267 , H03F2200/297 , H03F2200/451 , H03G3/3042
Abstract: A power amplifier circuit includes a first amplifier transistor, an input signal being supplied to a base of the first amplifier transistor, a first amplification signal obtained by amplifying the input signal being output from a collector of the first amplifier transistor; a first bias circuit that supplies a first current or a first voltage to the base of the first amplifier transistor; a second bias circuit that supplies a second current or a second voltage to the base of the first amplifier transistor; and a first resistor element that is connected in series between the base of the first amplifier transistor and the first bias circuit. The second bias circuit includes a diode, an impedance circuit, and a first capacitor element.
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公开(公告)号：US20210242842A1
公开(公告)日：2021-08-05
申请号：US17168618
申请日：2021-02-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hiroaki TOKUYA , Hideyuki SATO , Fumio HARIMA , Kenichi SHIMAMOTO , Satoshi TANAKA , Takayuki KAWANO , Ryoki SHIKISHIMA , Atsushi KUROKAWA
Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.
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Patent Agency Ranking
公开(公告)号：US20210242836A1
公开(公告)日：2021-08-05
申请号：US17167406
申请日：2021-02-04
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideyuki SATO , Koshi HIMEDA
IPC: H03F1/08 , H03F3/213 , H01L27/102 , H01L29/737 , H01L23/00
Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.
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公开(公告)号：US20250030383A1
公开(公告)日：2025-01-23
申请号：US18909281
申请日：2024-10-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi TANAKA , Hideyuki SATO , Yoshiaki SUKEMORI
Abstract: A power amplification module includes a carrier amplifier circuit; a carrier bias circuit that supplies a bias to the carrier amplifier circuit; a peak amplifier circuit; and a peak bias circuit that includes a first transistor having a collector or a drain connected to a reference potential and that supplies a bias to the peak amplifier circuit from an emitter or a source of the first transistor. The peak bias circuit is electrically connected to a current output circuit that outputs a predetermined current from the emitter or the source of the first transistor.
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公开(公告)号：US20210203288A1
公开(公告)日：2021-07-01
申请号：US17125227
申请日：2020-12-17
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yoshiaki SUKEMORI , Kenji TAHARA , Hideyuki SATO , Hisanori NAMIE
Abstract: A power amplifying module includes a first input terminal, a second input terminal, a first power amplifier, a stage matching circuit, a bypass line, and a second power amplifier. The first input terminal receives a first input signal in a first operation mode. The second input terminal receives a second input signal in a second operation mode which is different from the first operation mode. The first power amplifier amplifies the first input signal and outputs a first amplified signal. The stage matching circuit is disposed downstream of the first power amplifier and receives the first amplified signal. The bypass line outputs the second input signal to the inside of the stage matching circuit not through the first power amplifier. The second power amplifier is disposed downstream of the stage matching circuit, and amplifies the first amplified signal or the second input signal and outputs a second amplified signal.
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公开(公告)号：US20250105794A1
公开(公告)日：2025-03-27
申请号：US18894479
申请日：2024-09-24
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Jun ENOMOTO , Shohei IMAI , Hideyuki SATO
Abstract: A substrate and a chip device mounted on a main surface of the substrate are provided. The chip device is provided with a first differential amplifier including a first carrier amplifier and a second carrier amplifier, and a second differential amplifier including a first peak amplifier and a second peak amplifier. In the chip device, the first carrier amplifier and the second carrier amplifier are disposed side by side in a first direction, the first carrier amplifier and the first peak amplifier are disposed side by side in a second direction different from the first direction, the first peak amplifier and the second peak amplifier are disposed side by side in the first direction, and the second carrier amplifier and the second peak amplifier are disposed side by side in the second direction.
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公开(公告)号：US20240235488A1
公开(公告)日：2024-07-11
申请号：US18403131
申请日：2024-01-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi TANAKA , Yuri HONDA , Hideyuki SATO
CPC classification number: H03F1/0288 , H03F1/56 , H03F3/211 , H03F2200/387
Abstract: A power amplifier circuit includes: a first amplifier; a second amplifier; and an impedance inverter that delays an output of the first amplifier by a time equivalent to ¼ of a wavelength of a transmission line, and combines the output of the first amplifier delayed by the impedance inverter and an output of the second amplifier and outputs a combined output. The impedance inverter includes a plurality of unit circuits each constituted by an inductor and a capacitor, the plurality of unit circuits are cascade-connected to an output side of the first amplifier, an element included in each unit circuit of the plurality of unit circuits is connected in series to the element of an adjacent unit circuit, and another element included in each unit circuit of the plurality of unit circuits is connected between one end of the element of the same unit circuit.
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