公开(公告)号：US20200161226A1

公开(公告)日：2020-05-21

申请号：US16749904

申请日：2020-01-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Kazuya KOBAYASHI ,  Yuichi SANO

IPC: H01L23/495 ,  H01L23/00

Abstract: A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.

公开(公告)号：US20180247895A1

公开(公告)日：2018-08-30

申请号：US15903908

申请日：2018-02-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuichi SANO ,  Atsushi KUROKAWA ,  Kazuya KOBAYASHI

IPC: H01L23/532 ,  H01L23/485

CPC classification number: H01L23/53252 ,  H01L23/485

Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.

公开(公告)号：US20230395542A1

公开(公告)日：2023-12-07

申请号：US18452668

申请日：2023-08-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya KOBAYASHI ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Isao OBU ,  Yuichi SAITO

IPC: H01L23/00 ,  H01L23/31 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L24/05 ,  H01L28/40 ,  H01L23/3171 ,  H01L27/0658 ,  H01L27/0676 ,  H01L2224/05558 ,  H01L28/20 ,  H01L23/3192 ,  H01L27/0664 ,  H01L2224/05573 ,  H01L2224/04105 ,  H01L23/528

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

公开(公告)号：US20200243671A1

公开(公告)日：2020-07-30

申请号：US16752560

申请日：2020-01-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Kazuya KOBAYASHI

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L23/00 ,  H01L29/205 ,  H01L29/45

Abstract: A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.

公开(公告)号：US20200235026A1

公开(公告)日：2020-07-23

申请号：US16749886

申请日：2020-01-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Koshi HIMEDA ,  Kazuya KOBAYASHI

IPC: H01L23/367 ,  H01L27/082 ,  H01L27/02 ,  H01L23/528 ,  H01L29/08 ,  H01L29/205 ,  H01L29/10 ,  H01L29/737 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L23/00 ,  H01L29/165

Abstract: A semiconductor apparatus includes a substrate, plural transistor groups disposed on the substrate, an insulating film, and a metal member. Each of the plural transistor groups includes plural unit transistors arranged in a first direction within a plane of a top surface of the substrate. The plural transistor groups are arranged in a second direction perpendicular to the first direction. The insulating film covers the plural unit transistors and includes at least one cavity. The metal member is disposed on the insulating film and is electrically connected to the plural unit transistors via the at least one cavity. A heat transfer path is formed by a metal in a region from each of the plural unit transistors to a top surface of the metal member. Thermal resistance values of the heat transfer paths are different from each other among the plural unit transistors.

公开(公告)号：US20200168725A1

公开(公告)日：2020-05-28

申请号：US16681640

申请日：2019-11-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Koshi HIMEDA ,  Kazuya KOBAYASHI

IPC: H01L29/73 ,  H01L29/732 ,  H01L29/417 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.

公开(公告)号：US20200006265A1

公开(公告)日：2020-01-02

申请号：US16452637

申请日：2019-06-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya KOBAYASHI ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Isao OBU ,  Yuichi SAITO

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/31 ,  H01L27/06 ,  H01L23/528

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.