公开(公告)号：US20210202180A1

公开(公告)日：2021-07-01

申请号：US17131898

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki FUKUNAGA ,  Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/12 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a third segregation by each of metal elements of a first segregation and a second segregation is provided at each of a first corner region in which an end in a length direction in which the first segregation is provided overlaps an end in a width direction in which the second segregation is provided in a first internal electrode layer, and a second corner region in which an end in the length direction in which the second segregation is provided overlaps an end in the width direction in which the second segregation is provided in a second internal electrode layer.

公开(公告)号：US20240087814A1

公开(公告)日：2024-03-14

申请号：US18519243

申请日：2023-11-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/1218 ,  H01G4/2325 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US20230352243A1

公开(公告)日：2023-11-02

申请号：US18218300

申请日：2023-07-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/1218 ,  H01G4/012

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20230178305A1

公开(公告)日：2023-06-08

申请号：US18103054

申请日：2023-01-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/248 ,  H01G4/12 ,  H01G4/008

CPC classification number: H01G4/30 ,  H01G4/2325 ,  H01G4/248 ,  H01G4/1218 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US20220102077A1

公开(公告)日：2022-03-31

申请号：US17487349

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20210020377A1

公开(公告)日：2021-01-21

申请号：US16925350

申请日：2020-07-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Masahiro WAKASHIMA

IPC: H01G4/30 ,  H01G2/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a ceramic multilayer body including ceramic layers and internal electrodes that are layered, main surfaces, side surfaces, and end surfaces, a conductor layer covering each of the end surfaces of the ceramic multilayer body and electrically connected to the internal electrodes, an insulating layer covering the conductor layer, and an external electrode electrically connected to the conductor layer. The conductor layer includes a portion that extends to a portion of each of the main surfaces of the ceramic multilayer body.

公开(公告)号：US20250166925A1

公开(公告)日：2025-05-22

申请号：US19027935

申请日：2025-01-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US20220148812A1

公开(公告)日：2022-05-12

申请号：US17495853

申请日：2021-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu TSUTSUI ,  Yuta KUROSU ,  Daiki FUKUNAGA ,  Yuta SAITO ,  Masahiro WAKASHIMA

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008 ,  H01G13/00 ,  C04B35/468

Abstract: A method of manufacturing a multilayer ceramic capacitor includes printing an internal electrode pattern on a dielectric layer, forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed, laminating dielectric layers to form a multilayer body, exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body, removing at least a portion of the exposed dielectric pattern, and forming a dielectric gap layer on the side surface.

公开(公告)号：US20220102079A1

公开(公告)日：2022-03-31

申请号：US17487385

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

公开(公告)号：US20210202179A1

公开(公告)日：2021-07-01

申请号：US17131896

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta SAITO ,  Yuta KUROSU ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/12 ,  H01G4/248

Abstract: In a multilayer ceramic capacitor, a first segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end in a length direction of a first internal electrode layer not connected to a second external electrode and an end in a length direction of a second internal electrode layer not connected to a first external electrode. A second segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end of the first internal electrode layer in a width direction and an end of the second internal electrode layer in the width direction.