公开(公告)号：US20240079281A1

公开(公告)日：2024-03-07

申请号：US18239447

申请日：2023-08-29

Applicant: NEC Corporation

Inventor： Suguru WATANABE ,  Kunihiko ISHIHARA ,  Katsumi KIKUCHI

IPC: H01L23/053 ,  H01L23/498 ,  H01R12/70 ,  H01R12/71 ,  H01R13/24 ,  H10N69/00

CPC classification number: H01L23/053 ,  H01L23/49822 ,  H01R12/7005 ,  H01R12/714 ,  H01R13/2421 ,  H10N69/00 ,  H01L24/16 ,  H01L2224/16225

Abstract: A quantum device includes a quantum chip including a superconducting quantum circuit; an interposer including mounting the quantum chip on a first surface thereof; a housing having openings penetrating from a first surface of the housing opposing a second surface of the interposer to a second surface of the housing with probe pins housed in the opening, a board with a first surface facing the second surface of the housing; and one or more spacers between the first surface of the housing and the second surface of the interposer to ensure a clearance between the first surface of the housing and the second surface of the interposer facing the first surface of the housing.

公开(公告)号：US20230008193A1

公开(公告)日：2023-01-12

申请号：US17850052

申请日：2022-06-27

Applicant: NEC Corporation

Inventor： Suguru WATANABE ,  Kunihiko Ishihara ,  Katsumi Kikuchi

IPC: H01L39/22 ,  G06N10/40

Abstract: A quantum device capable of preventing contacts from being displaced is provided. A quantum device includes a quantum element in which a quantum circuit is provided, a socket including contacts and a housing, the contacts being in contact with a terminal of the quantum element, and the housing supporting the contacts, and a board including a board substrate. At least one of the housing and the board substrate includes a hole, another one of the housing and the board substrate includes a fixing part disposed inside the hole and a body part other than the fixing part, and the fixing part and the body part are integrally formed.

公开(公告)号：US20210407928A1

公开(公告)日：2021-12-30

申请号：US17357233

申请日：2021-06-24

Applicant: NEC Corporation

Inventor： Kenji NANBA ,  Ayami YAMAGUCHI ,  Akira MIYATA ,  Katsumi KIKUCHI ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU

IPC: H01L23/552 ,  H01L23/498

Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.

公开(公告)号：US20240136274A1

公开(公告)日：2024-04-25

申请号：US18226866

申请日：2023-07-26

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H01L23/498 ,  G06N10/40 ,  H01L23/13 ,  H01L23/367 ,  H10N60/81 ,  H10N69/00

CPC classification number: H01L23/49888 ,  G06N10/40 ,  H01L23/13 ,  H01L23/3677 ,  H10N60/815 ,  H10N69/00 ,  H01L23/36

Abstract: A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device includes a quantum chip and an interposer on which the quantum chip is located. The interposer includes an interposer substrate and an interposer wiring layer. The interposer wiring layer is disposed on a surface of the interposer substrate on a side on which the quantum chip is located. The interposer wiring layer includes, in at least a part thereof, a superconducting material layer formed of a superconducting material and a non-superconducting material layer formed of a non-superconducting material.

公开(公告)号：US20230345844A1

公开(公告)日：2023-10-26

申请号：US18007772

申请日：2020-06-05

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H10N60/81 ,  H01P7/08 ,  G06N10/40

CPC classification number: H10N60/815 ,  H01P7/082 ,  G06N10/40

Abstract: Provided is a quantum device capable of improving cooling performance. A quantum device includes a quantum chip configured to perform information processing using a quantum state, and an interposer on which the quantum chip is mounted, and the quantum chip is arranged inside a recess 31 formed in a sample stage having a cooling function, and a part of the interposer is in contact with the sample stage. The quantum chip may have a first surface mounted on the interposer and a second surface opposite to the first surface, and at least a part of the second surface may be in contact with an inner surface of the recess.

公开(公告)号：US20230237362A1

公开(公告)日：2023-07-27

申请号：US18007769

申请日：2020-06-05

Applicant: NEC Corporation

Inventor： Akira MIYATA ,  Katsumi KIKUCHI ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Tomohiro YAMAJI ,  Tsuyoshi YAMAMOTO ,  Yoshihito HASHIMOTO

IPC: G06N10/40 ,  G01R33/035

CPC classification number: G06N10/40 ,  G01R33/0354

Abstract: Provided is a quantum device capable of suppressing reduction in performance of quantum bit even when a quantum chip is flip-chip mounted on an interposer. A quantum chip (10) is flip-chip mounted on an interposer (20) by a bump (30). A coplanar line (12) coupling adjacent quantum bits is formed on the quantum chip (10). A gap (22) is provided, in the interposer (20), at a location facing a center conductor (12a) of the coplanar line (12). A second ground electrode (24) is formed around gap (22). The interposer (20) has a connection electrode (40) connecting the second ground electrode (24) around the gap (22). A bump (30A) formed in the vicinity of the connection electrode (40) is connected to the first ground electrode (12b) and the second ground electrode (24).

公开(公告)号：US20230034867A1

公开(公告)日：2023-02-02

申请号：US17789308

申请日：2020-01-10

Applicant: NEC Corporation

Inventor： Suguru WATANABE ,  Takanori Nishi

IPC: H01L23/14 ,  H01L23/498 ,  H01L21/48

Abstract: A wiring substrate capable of providing a through electrode having an insulating layer with a small dielectric loss is provided. A wiring substrate (50) includes a silicon substrate (40) formed of silicon whose electrical resistivity is 1000 Ω·cm or larger and a through electrode (100) formed in the silicon substrate (40). The through electrode (100) is formed of a central conductor (110) that penetrates through the silicon substrate (40) and an external conductor (120, 130, 140) formed around the central conductor (110). The central conductor (110) and the external conductor (120, 130, 140) are electrically insulated from each other by the silicon substrate (40).

公开(公告)号：US20170200985A1

公开(公告)日：2017-07-13

申请号：US15315664

申请日：2015-04-22

Applicant: NEC Corporation

Inventor： Hiroaki FUKUNISHI ,  Kenji KOBAYASHI ,  Suguru WATANABE ,  Osamu ISHIBASHI ,  Hiroshi KAJITANI ,  Kazuhisa SUNAGA ,  Hideyuki SUGITA ,  Atsumasa SAWADA ,  Ayami TANABE

IPC: H01M10/44 ,  H02J7/00 ,  H01M10/0525

CPC classification number: H01M10/44 ,  H01M10/0525 ,  H01M10/613 ,  H02J7/0052 ,  H02J7/0063 ,  H02J2007/0067

Abstract: A pulsed discharge device according to an exemplary aspect of the present invention includes a controller configured to determine an interruption time to a discharge time based on a predetermined time ratio between the discharge time and the interruption time when performing a pulsed discharge to repeat alternately a discharge and a pause in discharging of a chemical battery.