公开(公告)号：US20250104333A1

公开(公告)日：2025-03-27

申请号：US18971781

申请日：2024-12-06

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Magnus ANDERSSON ,  Ian KWONG ,  Edward BIDDULPH

IPC: G06T15/06 ,  G06T15/00 ,  G06T15/40

Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.

公开(公告)号：US20250104332A1

公开(公告)日：2025-03-27

申请号：US18971672

申请日：2024-12-06

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00 ,  G06T17/00

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20250095277A1

公开(公告)日：2025-03-20

申请号：US18964127

申请日：2024-11-29

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Ronald Charles BABICH ,  William Parsons Newhall

IPC: G06T15/06 ,  G06F9/48 ,  G06F9/50 ,  G06T17/10

Abstract: Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.

公开(公告)号：US20250046004A1

公开(公告)日：2025-02-06

申请号：US18922644

申请日：2024-10-22

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06F9/50 ,  G06T3/4007 ,  G06T9/00 ,  G06T15/08 ,  G06T17/10

Abstract: Ray tracing hardware accelerators supporting motion blur and moving/deforming geometry are disclosed. For example, dynamic objects in an acceleration data structure are encoded with temporal and spatial information. The hardware includes circuitry that test ray intersections against moving/deforming geometry by applying such temporal and spatial information. Such circuitry accelerates the visibility sampling of moving geometry, including rigid body motion and object deformation, and its associated moving bounding volumes to a performance similar to that of the visibility sampling of static geometry.

公开(公告)号：US20240303906A1

公开(公告)日：2024-09-12

申请号：US18668599

申请日：2024-05-20

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  James ROBERTSON ,  Magnus ANDERSON

IPC: G06T15/06 ,  G06F9/50 ,  G06T1/20 ,  G06T15/00 ,  G06T15/08 ,  G06T17/10

CPC classification number: G06T15/06 ,  G06F9/5027 ,  G06T1/20 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10 ,  G06T2210/12

Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.

公开(公告)号：US20240095995A1

公开(公告)日：2024-03-21

申请号：US17946201

申请日：2022-09-16

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Magnus ANDERSSON ,  Ian KWONG ,  Edward BIDDULPH

IPC: G06T15/06 ,  G06T15/00 ,  G06T15/30

CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T15/30 ,  G06T2210/12 ,  G06T2210/21

Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.

公开(公告)号：US20240009226A1

公开(公告)日：2024-01-11

申请号：US18471634

申请日：2023-09-21

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: A61K31/714 ,  A61K31/4415 ,  A61K31/198 ,  A61K31/197 ,  A61K31/14 ,  A61K31/385 ,  A61K31/205 ,  A61K31/51 ,  A61K31/4188 ,  A61K31/519 ,  A61K31/525 ,  A61K31/19

CPC classification number: A61K31/714 ,  A61K31/4415 ,  A61K31/198 ,  A61K31/197 ,  A61K31/14 ,  A61K31/385 ,  A61K31/205 ,  A61K31/51 ,  A61K31/4188 ,  A61K31/519 ,  A61K31/525 ,  A61K31/19

Abstract: Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.

公开(公告)号：US20220292759A1

公开(公告)日：2022-09-15

申请号：US17749951

申请日：2022-05-20

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06T15/08 ,  G06F9/50 ,  G06T3/40 ,  G06T9/00 ,  G06T17/10

Abstract: Ray tracing hardware accelerators supporting motion blur and moving/deforming geometry are disclosed. For example, dynamic objects in an acceleration data structure are encoded with temporal and spatial information. The hardware includes circuitry that test ray intersections against moving/deforming geometry by applying such temporal and spatial information. Such circuitry accelerates the visibility sampling of moving geometry, including rigid body motion and object deformation, and its associated moving bounding volumes to a performance similar to that of the visibility sampling of static geometry.

公开(公告)号：US20210390760A1

公开(公告)日：2021-12-16

申请号：US16901847

申请日：2020-06-15

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John Burgess

IPC: G06T15/06 ,  G06T15/08 ,  G06T17/10 ,  G06T3/40 ,  G06T9/00 ,  G06F9/50

Abstract: Ray tracing hardware accelerators supporting motion blur and moving/deforming geometry are disclosed. For example, dynamic objects in an acceleration data structure are encoded with temporal and spatial information. The hardware includes circuitry that test ray intersections against moving/deforming geometry by applying such temporal and spatial information. Such circuitry accelerates the visibility sampling of moving geometry, including rigid body motion and object deformation, and its associated moving bounding volumes to a performance similar to that of the visibility sampling of static geometry.

公开(公告)号：US20250095276A1

公开(公告)日：2025-03-20

申请号：US18962764

申请日：2024-11-27

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06F9/30 ,  G06F9/50 ,  G06T15/08 ,  G06T17/00

Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.