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Patent Agency Ranking
公开(公告)号：US20240095994A1
公开(公告)日：2024-03-21
申请号：US17946193
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
CPC classification number: G06T15/06 , G06T15/005 , G06T15/40 , G06T2210/12 , G06T2210/21
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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公开(公告)号：US20250104333A1
公开(公告)日：2025-03-27
申请号：US18971781
申请日：2024-12-06
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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公开(公告)号：US20240095995A1
公开(公告)日：2024-03-21
申请号：US17946201
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
CPC classification number: G06T15/06 , G06T15/005 , G06T15/30 , G06T2210/12 , G06T2210/21
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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公开(公告)号：US20240355039A1
公开(公告)日：2024-10-24
申请号：US18761820
申请日：2024-07-02
Applicant: NVIDIA Corporation
Inventor： Samuli LAINE , Tero KARRAS , Timo AILA , Robert OHANNESSIAN , William Parsons NEWHALL, Jr. , Greg MUTHLER , Ian KWONG , Peter NELSON , John BURGESS
CPC classification number: G06T15/06 , G06T15/005
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
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公开(公告)号：US20240095993A1
公开(公告)日：2024-03-21
申请号：US17946093
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
CPC classification number: G06T15/06 , G06T15/005
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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