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    COMBINED ON-PACKAGE AND OFF-PACKAGE MEMORY SYSTEM
    11.
    发明申请
    COMBINED ON-PACKAGE AND OFF-PACKAGE MEMORY SYSTEM 有权

    公开(公告)号：US20220342595A1

    公开(公告)日：2022-10-27

    申请号：US17237165

    申请日：2021-04-22

    Applicant: NVIDIA Corporation

    Inventor： Niladrish Chatterjee ,  James Michael O'Connor ,  Donghyuk Lee ,  Gaurav Uttreja ,  Wishwesh Anil Gandhi

    IPC: G06F3/06 ,  G06F12/06 ,  G06F12/10

    Abstract: A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.

    Techniques for performing matrix computations using hierarchical representations of sparse matrices
    13.
    发明授权
    Techniques for performing matrix computations using hierarchical representations of sparse matrices 有权

    公开(公告)号：US12211080B2

    公开(公告)日：2025-01-28

    申请号：US17325116

    申请日：2021-05-19

    Applicant: NVIDIA CORPORATION

    Inventor： Hanrui Wang ,  James Michael O'Connor ,  Donghyuk Lee

    IPC: G06F16/901 ,  G06F17/16 ,  G06Q30/0601

    Abstract: One embodiment sets forth a technique for performing matrix operations. The technique includes traversing a tree structure to access one or more non-empty regions within a matrix. The tree structure includes a first plurality of nodes and a second plurality of nodes corresponding to non-empty regions in the matrix. The first plurality of nodes includes a first node representing a first region and one or more second nodes that are children of the first node and represent second region(s) with an equal size formed within the first region. The second plurality of nodes include a third node representing a third region and one or more fourth nodes that are children of the third node and represent fourth region(s) with substantially equal numbers of non-zero matrix values formed within the third region. The technique also includes performing matrix operation(s) based on the non-empty region(s) to generate a matrix operation result.

    Techniques for accelerating matrix multiplication computations using hierarchical representations of sparse matrices
    14.
    发明授权
    Techniques for accelerating matrix multiplication computations using hierarchical representations of sparse matrices 有权

    公开(公告)号：US12141229B2

    公开(公告)日：2024-11-12

    申请号：US17325120

    申请日：2021-05-19

    Applicant: NVIDIA CORPORATION

    Inventor： Hanrui Wang ,  James Michael O'Connor ,  Donghyuk Lee

    IPC: G06F17/16 ,  G06F9/50 ,  G06F16/901

    Abstract: One embodiment sets forth a technique for performing one or more matrix multiplication operations based on a first matrix and a second matrix. The technique includes receiving data associated with the first matrix from a first traversal engine that accesses nonzero elements included in the first matrix via a first tree structure. The technique also includes performing one or more computations on the data associated with the first matrix and the data associated with the second matrix to produce a plurality of partial results. The technique further includes combining the plurality of partial results into one or more intermediate results and storing the one or more intermediate results in a first buffer memory.

    Application partitioning for locality in a stacked memory system
    16.
    发明授权
    Application partitioning for locality in a stacked memory system 有权

    公开(公告)号：US12099453B2

    公开(公告)日：2024-09-24

    申请号：US17709031

    申请日：2022-03-30

    Applicant: NVIDIA Corporation

    Inventor： William James Dally ,  Carl Thomas Gray ,  Stephen W. Keckler ,  James Michael O'Connor

    IPC: G06F13/16 ,  G11C8/12 ,  H03K19/1776

    CPC classification number: G06F13/161 ,  G06F13/1673 ,  G06F13/1689 ,  G11C8/12 ,  H03K19/1776

    Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

    MEMORY STACKED ON PROCESSOR FOR HIGH BANDWIDTH
    19.
    发明公开
    MEMORY STACKED ON PROCESSOR FOR HIGH BANDWIDTH 审中-公开

    公开(公告)号：US20230275068A1

    公开(公告)日：2023-08-31

    申请号：US17683290

    申请日：2022-02-28

    Applicant: NVIDIA Corporation

    Inventor： William James Dally ,  Carl Thomas Gray ,  Stephen W. Keckler ,  James Michael O'Connor

    IPC: H01L25/065

    CPC classification number: H01L25/0657 ,  H01L2225/06565 ,  H01L27/11517

    Abstract: Embodiments of the present disclosure relate to memory stacked on processor for high bandwidth. Systems and methods are disclosed for providing a one-level memory for a processing system by stacking bulk memory on a processor die. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles, where each tile includes a processing unit, mapper, and tile network. Each memory die includes multiple memory tiles. The processing tile is coupled to each memory tile that is above or below the processing tile. The vertically aligned memory tiles comprise the local memory block for the processing tile. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

    TECHNIQUES FOR PERFORMING MATRIX COMPUTATIONS USING HIERARCHICAL REPRESENTATIONS OF SPARSE MATRICES
    20.
    发明申请
    TECHNIQUES FOR PERFORMING MATRIX COMPUTATIONS USING HIERARCHICAL REPRESENTATIONS OF SPARSE MATRICES 有权

    公开(公告)号：US20220374961A1

    公开(公告)日：2022-11-24

    申请号：US17325116

    申请日：2021-05-19

    Applicant: NVIDIA CORPORATION

    Inventor： Hanrui Wang ,  James Michael O'Connor ,  Donghyuk Lee

    IPC: G06Q30/06 ,  G06F16/901 ,  G06F17/16

    Abstract: One embodiment sets forth a technique for performing matrix operations. The technique includes traversing a tree structure to access one or more non-empty regions within a matrix. The tree structure includes a first plurality of nodes and a second plurality of nodes corresponding to non-empty regions in the matrix. The first plurality of nodes includes a first node representing a first region and one or more second nodes that are children of the first node and represent second region(s) with an equal size formed within the first region. The second plurality of nodes include a third node representing a third region and one or more fourth nodes that are children of the third node and represent fourth region(s) with substantially equal numbers of non-zero matrix values formed within the third region. The technique also includes performing matrix operation(s) based on the non-empty region(s) to generate a matrix operation result.

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