公开(公告)号：US20200302676A1

公开(公告)日：2020-09-24

申请号：US16893107

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C. BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20200050451A1

公开(公告)日：2020-02-13

申请号：US16101247

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Ronald Babich ,  John BURGESS ,  Jack CHOQUETTE ,  Tero KARRAS ,  Samuli LAINE ,  Ignacio LLAMAS ,  Gregory MUTHLER ,  William Parsons NEWHALL, JR.

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60

Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.

公开(公告)号：US20230410410A1

公开(公告)日：2023-12-21

申请号：US18239876

申请日：2023-08-30

Applicant: NVIDIA Corporation

Inventor： Samuli LAINE ,  Tero KARRAS ,  Greg MUTHLER ,  William Parsons Newhall, JR. ,  Ronald Charles BABACH, JR. ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T15/005 ,  G06T2210/21

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.

公开(公告)号：US20200160588A1

公开(公告)日：2020-05-21

申请号：US16749089

申请日：2020-01-22

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06T15/06

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.

公开(公告)号：US20200051315A1

公开(公告)日：2020-02-13

申请号：US16101180

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Samuli Laine ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS

IPC: G06T15/06 ,  G06T7/60 ,  G06T15/60 ,  G06F17/30

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20200050550A1

公开(公告)日：2020-02-13

申请号：US16101109

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Timo AILA ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL ,  Ronald Charles BABICH ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06F12/0875 ,  G06T15/06 ,  G06F17/30

Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.