公开(公告)号：US20140281383A1

公开(公告)日：2014-09-18

申请号：US13973952

申请日：2013-08-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Thomas Hastings Greer, III

IPC: G06F15/78

CPC classification number: G06F15/7864 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-, ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括处理器芯片，系统功能芯片和被配置为包括处理器芯片，系统功能芯片和互连电路的MCM封装。 处理器芯片被配置为包括第一接地参考的单端信令接口电路。 在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。 系统功能芯片被配置为包括第二单端信令接口电路和主机接口。 MCM封装中制造的第二组电迹线，用于将主机接口耦合到MCM封装的至少一个外部引脚。 在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

公开(公告)号：US20140253175A1

公开(公告)日：2014-09-11

申请号：US13787705

申请日：2013-03-06

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: H03K19/096

CPC classification number: H03K19/096

Abstract: A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches.

Abstract translation: 公开了一种用于将设计从边缘触发对接转换为两相非重叠计时的系统，方法和计算机程序产品。 该方法包括以下步骤：将包括第一锁存电路和第二锁存电路的一对锁存器耦合到组合逻辑电路的边沿触发触发器电路替换，并基于定时确定组合逻辑电路的中点 信息。 第二锁存电路被传播到组合逻辑电路的中点，并且两对非重叠时钟信号被提供给该对锁存器。

公开(公告)号：US20140232360A1

公开(公告)日：2014-08-21

申请号：US13770982

申请日：2013-02-19

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G05F1/563

CPC classification number: G05F1/563 ,  H02M3/1588 ,  H02M2001/0016 ,  H02M2001/0032 ,  H02M2003/1586 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A system and method are provided for estimating current. A current source is configured to generate a current and a pulsed sense enable signal is generated. An estimate of the current is generated and the estimate of the current is updated based on a first signal that is configured to couple the current source to an electric power supply and a second signal that is configured to couple the current source to aloud. A system includes the current source and a current prediction unit. The current source is configured to generate a current. The current prediction unit is coupled the current source and is configured to generate the estimate of the current and update the estimate of the current based on the first signal and the second signal.

Abstract translation: 提供了一种用于估计电流的系统和方法。 电流源被配置为产生电流并且产生脉冲检测使能信号。 产生电流的估计，并且基于被配置为将电流源耦合到电力供应的第一信号和被配置为大声耦合当前源的第二信号来更新电流的估计。 系统包括电流源和当前预测单元。 当前源被配置为生成电流。 当前预测单元耦合电流源，并被配置为基于第一信号和第二信号产生电流的估计并更新电流的估计。

公开(公告)号：US20140225579A1

公开(公告)日：2014-08-14

申请号：US13763516

申请日：2013-02-08

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G05F1/10

CPC classification number: G05F1/10 ,  H02M3/1582 ,  H02M3/1584 ,  H02M2001/008

Abstract: A system and method are provided for regulating a voltage at a load. A current source is configured to provide a current to a voltage control mechanism and the voltage control mechanism is configured to provide a portion of the current to the load. The current is generated based on the portion of the current that is provided to the load. A system includes the current source, an upstream controller, and the voltage control mechanism that is coupled to the load. The upstream controller is coupled to the current source and is configured to control a current that is generated by the current source based on a portion of the current that is provided to the load.

Abstract translation: 提供一种用于调节负载电压的系统和方法。 电流源被配置为向电压控制机构提供电流，并且电压控制机构被配置为向负载提供电流的一部分。 基于提供给负载的电流部分产生电流。 系统包括电流源，上游控制器和耦合到负载的电压控制机构。 上游控制器耦合到电流源，并被配置为基于提供给负载的电流的一部分来控制由电流源产生的电流。

公开(公告)号：US20140218001A1

公开(公告)日：2014-08-07

申请号：US13759964

申请日：2013-02-05

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G05F1/618

CPC classification number: G05F1/618 ,  G06F1/26 ,  H02M1/00 ,  H02M3/158 ,  H02M3/1582 ,  H02M3/1584

Abstract: A system and method are provided for generating non-overlapping enable signals. A peak voltage level is measured at an output of a current source that is configured to provide current to a voltage control mechanism. The non-overlapping enable signals are generated for the voltage control mechanism based on the peak voltage level. A system includes the current source, a downstream controller, and the voltage control mechanism that is coupled to the load. The current source is configured to provide current to the voltage control mechanism. The controller is configured to measure the peak voltage level at the output of the current source and generate the non-overlapping enable signals based on the peak voltage level. The non-overlapping enable signals provide a portion of the current to the load.

Abstract translation: 提供了一种用于产生不重叠使能信号的系统和方法。 在被配置为向电压控制机构提供电流的电流源的输出处测量峰值电压电平。 基于峰值电压电平为电压控制机构产生不重叠的使能信号。 系统包括电流源，下游控制器和耦合到负载的电压控制机构。 电流源被配置成向电压控制机构提供电流。 控制器被配置为测量电流源的输出处的峰值电压电平，并基于峰值电压电平产生不重叠的使能信号。 不重叠的使能信号将电流的一部分提供给负载。

公开(公告)号：US20130278315A1

公开(公告)日：2013-10-24

申请号：US13921138

申请日：2013-06-18

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Ge Yang

IPC: H03K3/36

CPC classification number: H03K3/36 ,  H03K3/012 ,  H03K3/356121

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the dock.

Abstract translation: 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可能被布防，并且在基座的上升沿触发置位或复位。

公开(公告)号：US10891538B2

公开(公告)日：2021-01-12

申请号：US15659371

申请日：2017-07-25

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/04 ,  G06F17/11 ,  G06F9/30 ,  G06F9/38 ,  G06N3/08 ,  G06N3/063 ,  G06F9/355 ,  G06F17/16 ,  G06F9/28

Abstract: A method, computer program product, and system perform computations using a processor. A first instruction including a first index vector operand and a second index vector operand is received and the first index vector operand is decoded to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array. The second index vector operand is decoded to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array. The first coordinate sets are summed with the second coordinate sets to produce output coordinate sets and the output coordinate sets are converted into a set of linear indices.

公开(公告)号：US10528864B2

公开(公告)日：2020-01-07

申请号：US15458799

申请日：2017-03-14

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G06F7/523 ,  G06N3/08

Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. A first vector comprising only non-zero weight values and first associated positions of the non-zero weight values within a 3D space is received. A second vector comprising only non-zero input activation values and second associated positions of the non-zero input activation values within a 2D space is received. The non-zero weight values are multiplied with the non-zero input activation values, within a multiplier array, to produce a third vector of products. The first associated positions are combined with the second associated positions to produce a fourth vector of positions, where each position in the fourth vector is associated with a respective product in the third vector. The products in the third vector are transmitted to adders in an accumulator array, based on the position associated with each one of the products.

公开(公告)号：US10128904B2

公开(公告)日：2018-11-13

申请号：US14748079

申请日：2015-06-23

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H04B3/36 ,  H03K19/017 ,  H04L25/02 ,  H04B1/56

Abstract: A repeater circuit is disclosed. The repeater circuit is coupled to a transmission line driven by a first transmitter circuit and configured to detect a signal transition from a first voltage level to a second voltage level at a first position on the transmission line. The repeater circuit then reinforces the signal transition from the second voltage level to a third voltage level at the first position on the transmission line without interrupting a current through the transmission line.

公开(公告)号：US20160380674A1

公开(公告)日：2016-12-29

申请号：US14748079

申请日：2015-06-23

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H04B3/36 ,  H04B1/56

CPC classification number: H04B3/36 ,  H03K19/01721 ,  H04B1/56 ,  H04L25/0272 ,  H04L25/0292

Abstract: A repeater circuit is disclosed. The repeater circuit is coupled to a transmission line driven by a first transmitter circuit and configured to detect a signal transition from a first voltage level to a second voltage level at a first position on the transmission line. The repeater circuit then reinforces the signal transition from the second voltage level to a third voltage level at the first position on the transmission line without interrupting a current through the transmission line.

Abstract translation: 公开了一种中继器电路。 中继器电路耦合到由第一发射机电路驱动的传输线路，并被配置为检测在传输线路上的第一位置处从第一电压电平到第二电压电平的信号转变。 然后，中继器电路加强从传输线上的第一位置处的第二电压电平到第三电压电平的信号转变，而不中断通过传输线的电流。