公开(公告)号：US20140351827A1

公开(公告)日：2014-11-27

申请号：US13899343

申请日：2013-05-21

Applicant: NVIDIA CORPORATION

Inventor： Ignacio LLAMAS

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: An application programming interface (API) provides various software constructs that allow a developer to assemble a processing pipeline having arbitrary structure and complexity. Once assembled, the processing pipeline is configured to include a set of interconnected pipestages. Those pipestages are associated with one or more different CTAs that may execute in parallel with one another on a parallel processing unit. The developer specifies the configuration of the pipestages, including the configuration of the different CTAs across all pipestages, as well as the different processing operations performed by each different CTA.

Abstract translation: 应用程序编程接口（API）提供各种软件结构，允许开发人员组装具有任意结构和复杂性的处理管道。 一旦组装，处理管道被配置为包括一组相互连接的管道。 这些管道与一个或多个可在并行处理单元上彼此并行执行的不同CTA相关联。 开发人员指定管道的配置，包括跨所有管道的不同CTA的配置，以及由不同CTA执行的不同处理操作。

公开(公告)号：US20140123144A1

公开(公告)日：2014-05-01

申请号：US13662274

申请日：2012-10-26

Applicant: NVIDIA CORPORATION

Inventor： Ignacio LLAMAS ,  Craig Ross DUTTWEILER ,  Jeffrey A. BOLZ ,  Daniel Elliot WEXLER

IPC: G06F9/54

CPC classification number: G06F9/52 ,  G06F9/546 ,  G06F2209/548

Abstract: One embodiment of the present invention enables threads executing on a processor to locally generate and execute work within that processor by way of work queues and command blocks. A device driver, as an initialization procedure for establishing memory objects that enable the threads to locally generate and execute work, generates a work queue, and sets a GP_GET pointer of the work queue to the first entry in the work queue. The device driver also, during the initialization procedure, sets a GP_PUT pointer of the work queue to the last free entry included in the work queue, thereby establishing a range of entries in the work queue into which new work generated by the threads can be loaded and subsequently executed by the processor. The threads then populate command blocks with generated work and point entries in the work queue to the command blocks to effect processor execution of the work stored in the command blocks.

Abstract translation: 本发明的一个实施例使得在处理器上执行的线程能够通过工作队列和命令块来本地生成和执行该处理器内的工作。 设备驱动程序作为用于建立使线程本地生成和执行工作的内存对象的初始化过程，生成工作队列，并将工作队列的GP_GET指针设置为工作队列中的第一个条目。 在初始化过程中，设备驱动程序还将工作队列的GP_PUT指针设置到工作队列中包含的最后一个空闲条目，从而在工作队列中建立一个可以加载线程生成的新工作的条目范围 并随后由处理器执行。 然后，线程将工作队列中的生成工作和点条目的命令块填充到命令块，以执行存储在命令块中的工作的处理器执行。

公开(公告)号：US20240211255A1

公开(公告)日：2024-06-27

申请号：US18596106

申请日：2024-03-05

Applicant: NVIDIA Corporation

Inventor： Ronald Charles BABICH, JR. ,  John BURGESS ,  Jack CHOQUETTE ,  Tero KARRAS ,  Samuli LAINE ,  Ignacio LLAMAS ,  Gregory MUTHLER ,  William Parsons NEWHALL, JR.

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F15/163 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/3004 ,  G06F9/3877 ,  G06F9/4843 ,  G06F15/163 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.

公开(公告)号：US20230237729A1

公开(公告)日：2023-07-27

申请号：US18129334

申请日：2023-03-31

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06T15/06

CPC classification number: G06T15/06

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.

公开(公告)号：US20200302676A1

公开(公告)日：2020-09-24

申请号：US16893107

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C. BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20200050451A1

公开(公告)日：2020-02-13

申请号：US16101247

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Ronald Babich ,  John BURGESS ,  Jack CHOQUETTE ,  Tero KARRAS ,  Samuli LAINE ,  Ignacio LLAMAS ,  Gregory MUTHLER ,  William Parsons NEWHALL, JR.

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60

Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.

公开(公告)号：US20140351826A1

公开(公告)日：2014-11-27

申请号：US13899323

申请日：2013-05-21

Applicant: NVIDIA CORPORATION

Inventor： Ignacio LLAMAS

IPC: G06F9/48

CPC classification number: G06F9/3851 ,  G06F9/3826 ,  G06F9/3887

Abstract: An application programming interface (API) provides various software constructs that allow a developer to assemble a processing pipeline having arbitrary structure and complexity. Once assembled, the processing pipeline is configured to include a set of interconnected pipestages. Those pipestages are associated with one or more different CTAs that may execute in parallel with one another on a parallel processing unit. The developer specifies the configuration of the pipestages, including the configuration of the different CTAs across all pipestages, as well as the different processing operations performed by each different CTA.