-
公开(公告)号：US20240219453A1
公开(公告)日：2024-07-04
申请号：US18149536
申请日：2023-01-03
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Paul Wielage
IPC: G01R31/28
CPC classification number: G01R31/2837 , G01R31/2841 , G01R31/2843
Abstract: Various embodiments relate to a method of testing a plurality of devices of the same type wherein each of the plurality of devices of the same type include a built-in self-test device, including: randomly generating, by a processor, stimulus parameters; applying, by the built-in self-test devices, the generated stimulus parameters N times to the plurality of devices of the same type; measuring, by the plurality of devices of the same type, a response of the plurality of devices of the same type to the generated stimulus parameters to produce M×N response outputs, where M is a number of the plurality of devices of the same type; calculating, by the processor, a defect likelihood for a test set of the plurality of identical devices based upon a mean of a reference set of the plurality of identical devices response outputs, a mean of the test set response outputs, a standard deviation of reference set response outputs, and a standard deviation of the test set response outputs; determining, by the processor, that the defect likelihood for the test set is greater than a first threshold value; applying, by the processor, an initial step of a directed random search algorithm to update stimulus parameters in response to determining that the defect likelihood is greater than the first threshold; applying, by the built-in self-test devices, the updated stimulus parameters N times to the plurality of devices of the same type; measuring, by the plurality of devices of the same type, a response of the plurality of devices of the same type to the updated stimulus parameters to produce M×N updated response outputs; calculating, by the processor, a defect likelihood for the test set based upon a mean of the reference set updated response outputs, a mean of the test set updated response outputs, a standard deviation of reference set updated response outputs, and a standard deviation of the test set updated response outputs; and determining, by the processor, that the defect likelihood for the test set is greater than a second threshold, wherein the second threshold is greater than the first threshold.
-
公开(公告)号：US11502843B2
公开(公告)日：2022-11-15
申请号：US16237633
申请日：2018-12-31
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: This specification discloses devices and methods for a security concept that includes an immobile hardware token (e.g., a “wall token” that is fixed within a wall) which ensures that the more sensitive actions of electronic banking (e.g., money transfers of large sums to foreign bank accounts) can only be done from the account owner's home, but not from a remote place. However, other less sensitive (and lower security risk) actions can still be done from anywhere else. In some embodiments, the hardware token includes sensors to ensure that the token is not moved or tampered with, interfaces to provide distance bounding, and a crypto-processor to provide secure authentication. The distance bounding can be used to determine if the authentication device is in close proximity to the hardware token, which can in turn ensure that the authentication device is within the account owner's home.
-
公开(公告)号：US20220327209A1
公开(公告)日：2022-10-13
申请号：US17301679
申请日：2021-04-12
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.
-
公开(公告)号：US20220158820A1
公开(公告)日：2022-05-19
申请号：US17451198
申请日：2021-10-18
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Andreas Lentz , Fabrice Poulard
IPC: H04L9/06
Abstract: An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.
-
公开(公告)号：US20210366566A1
公开(公告)日：2021-11-25
申请号：US17315927
申请日：2021-05-10
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: G11C29/42 , G11C29/44 , G11C29/18 , G11C29/14 , H03K19/173
Abstract: The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.
-
Patent Agency Ranking
公开(公告)号：US11100219B2
公开(公告)日：2021-08-24
申请号：US16417858
申请日：2019-05-21
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: G01R31/3177 , G01R31/317 , G06F11/26 , G06F11/263 , G06F21/55
Abstract: A method and device for detecting a malicious circuit on an integrated circuit (IC) device is provided. The method includes generating a plurality of test patterns on the IC. A scan test circuit and the plurality of test patterns are used to test don't care bits of a function under test on the integrated circuit. Scan out data from the scan test circuit is provided in response to the plurality of test patterns. The scan out data is stored in a memory on the integrated circuit. The scan out data is monitored over a predetermined time period. If it is determined that a characteristic of the scan out data has changed within the predetermined time period, an indication that a malicious circuit has been detected is output. The device includes circuitry for performing the method in the field.
-
公开(公告)号：US20210237688A1
公开(公告)日：2021-08-05
申请号：US16781560
申请日：2020-02-04
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: According to certain examples, a circuit-based wireless communications system provides secure access to a vehicle by way of certain circuitry configure to compare a first RF background observed for a vehicle-located RF receiver that is part of a vehicle-located circuit secured to a vehicle, with a second RF background observed for a wireless-communications vehicle-access circuit that includes another RF receiver. In response, a distance metric is generated to indicate a degree of similarity between the first RF background and the second RF background, and based on whether this metric satisfies a threshold, access to the vehicle may be granted via the wireless-communications vehicle-access circuit.
-
公开(公告)号：US10890933B2
公开(公告)日：2021-01-12
申请号：US16591739
申请日：2019-10-03
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: The disclosure relates to voltage regulators and more specially voltage regulators including error detection and correction mechanisms. Example embodiments include a voltage regulator comprising: an input arranged to receive a trim signal used to specify a target voltage at an output of the regulator; a comparator arranged to compare a voltage derived from the trim signal to the voltage at the output of the regulator; a filter arranged to filter an output of the comparator; a checksum module comprising first and second portions arranged to calculate first and second checksums respectively from a plurality of states associated with the voltage regulator and to provide an error signal equal to the difference between the first and second checksums; and an adjustment module arranged to receive the error signal and adjust one or more of the plurality of states if the error signal is non-zero.
-
公开(公告)号：US10823781B1
公开(公告)日：2020-11-03
申请号：US16581869
申请日：2019-09-25
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: G01R31/28 , G01R31/317 , G01R31/3177 , G11C29/12 , G01R31/319 , G01R31/3187
Abstract: Embodiments are directed to apparatuses and methods for providing a logic built-in self-test (LBIST) using an LBIST logic circuit and an auxiliary logic circuit. An example method includes using switch circuitry in an integrated circuit (IC) to change modes of operation associated with functional logic circuit, the modes of operation including an LBIST mode and an application mode, and to provide an internally generated digital clock signal to the functional logic circuitry and an LBIST logic circuit in response to the LBIST mode. The method further includes performing an LBIST using the internally generated digital clock signal, the LBIST logic circuit to test select nodes in the IC via control of the functional logic circuitry and via application of digital logic sequences provided as inputs to the I/O pad cells of the IC.
-
公开(公告)号：US20190318083A1
公开(公告)日：2019-10-17
申请号：US16417858
申请日：2019-05-21
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: G06F21/55 , G01R31/3177
Abstract: A method and device for detecting a malicious circuit on an integrated circuit (IC) device is provided. The method includes generating a plurality of test patterns on the IC. A scan test circuit and the plurality of test patterns are used to test don't care bits of a function under test on the integrated circuit. Scan out data from the scan test circuit is provided in response to the plurality of test patterns. The scan out data is stored in a memory on the integrated circuit. The scan out data is monitored over a predetermined time period. If it is determined that a characteristic of the scan out data has changed within the predetermined time period, an indication that a malicious circuit has been detected is output. The device includes circuitry for performing the method in the field.
-
-
-
-
-
-
-
-
-
Search Results
80
records
(took 0.02 seconds)
