公开(公告)号：US10437666B2

公开(公告)日：2019-10-08

申请号：US14820396

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G11C29/50 ,  G06F11/10 ,  G11C11/419 ,  G11C29/42 ,  G11C29/52 ,  G11C29/04

Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.

公开(公告)号：US20170288927A1

公开(公告)日：2017-10-05

申请号：US15443982

申请日：2017-02-27

Applicant: NXP B.V.

Inventor： Nur Engin ,  Audrey Christine Andrée Cuenin

IPC: H04L27/26 ,  H04L25/49 ,  H04L5/00

CPC classification number: H04L27/2623 ,  H04L5/0064 ,  H04L25/49 ,  H04L27/2601

Abstract: A signal processing circuit comprising a clip-generation-block. The clip-generation-block is configured to receive an input-signal; and determine a clip-signal that comprises only values of the input-signal that exceed a clipping-threshold. The signal processing circuit also comprises a scaling-block configured to apply a scaling-factor to the clip-signal in order to generate a scaled-clip-signal, wherein the scaling-factor is greater than one; and an adder configured to provide a clipped-signal based on a difference between the scaled-clip-signal and the input signal.

公开(公告)号：US09778983B2

公开(公告)日：2017-10-03

申请号：US14820417

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/419 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C11/419 ,  G11C29/52

Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.