公开(公告)号：US20200044775A1

公开(公告)日：2020-02-06

申请号：US16051903

申请日：2018-08-01

Applicant: NXP B.V.

Inventor： Semih Serbetli ,  Nur Engin

IPC: H04L1/00

Abstract: Aspects of the present disclosure are directed to decoding signals susceptible to communication errors. As may be implemented in accordance with one or more embodiments, an input signal is decoded to produce a first decoded output, which is subsequently encoded, and error characteristics of the encoded first decoded output are assessed. The input signal is again decoded (e.g., with a delay), using the encoded first decoded output and the assessed error characteristics thereof to assess a reliability characteristic of bits in the input signal. A second decoded output is then provided with errors corrected therein based on the assessed reliability characteristic.

公开(公告)号：US20170039102A1

公开(公告)日：2017-02-09

申请号：US14820396

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C11/419 ,  G11C29/42 ,  G11C29/50 ,  G11C29/52 ,  G11C2029/0411

Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.

Abstract translation: 根据本发明的实施例，公开了一种IC器件。 在本实施例中，IC器件包括静态随机存取存储器（SRAM）的位单元阵列，多级数字化模块，被配置为从比特单元阵列中的比特单元生成值范围内的值， 包括多于两个离散值的值的范围，被配置为存储所生成的值的输出缓冲器，以及被配置为基于所存储的值输出误差校正值的纠错码（ECC）解码器。

公开(公告)号：US20170039103A1

公开(公告)日：2017-02-09

申请号：US14820417

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G06F11/10 ,  G11C11/419 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C11/419 ,  G11C29/52

Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

Abstract translation: 公开了一种包括耦合到封装逻辑的SRAM模块的集成电路（IC）装置。 包装器逻辑包括纠错码（ECC）编码器，其被配置为根据ECC编码方案对输入数据进行编码并将编码的输入数据输出到SRAM模块; ECC解码器，被配置为解码从SRAM模块接收的输出数据，输出 解码的输出数据和写解码信息返回到SRAM模块，耦合到ECC解码器的错误控制器，其被配置为根据ECC编码方案来控制ECC解码器;以及中央控制器，耦合到包装器的组件 逻辑和SRAM模块，以便控制包装逻辑和SRAM模块的组件之间的操作。

公开(公告)号：US09425922B2

公开(公告)日：2016-08-23

申请号：US14461030

申请日：2014-08-15

Applicant: NXP B.V.

Inventor： Nur Engin

IPC: H04L1/00 ,  H03M7/00 ,  H03M13/29 ,  H03M13/37 ,  H03M13/00

CPC classification number: H04L1/0054 ,  H03M7/00 ,  H03M7/3082 ,  H03M13/2957 ,  H03M13/3776 ,  H03M13/6325 ,  H03M13/6505 ,  H03M13/6588 ,  H04L1/005 ,  H04L1/0071 ,  H04L1/208

Abstract: A receiver, including: a posteriori probability demodulator configured to receive an input digital signal and output demodulated data; a deinterleaver configured to deinterleave the demodulated data; a forward error correction (FEC) decoder configured to error correct the demodulated data; a FEC encoder configured to encode the error corrected demodulated data; an interleaver configured to interleave the FEC encoded data and output the interleaved FEC encoded data to the posteriori probability demodulator; and a symbol compressor/decompressor configured to compress symbol data from the a posteriori demodulator and store the compressed data in a symbol memory and configured to decompress compressed symbol data stored in the symbol memory.

Abstract translation: 一种接收机，包括：后验概率解调器，被配置为接收输入数字信号并输出​​解调数据; 解交织器，被配置为对所解调的数据进行解交织; 配置为纠错解调数据的前向纠错（FEC）解码器; FEC编码器，被配置为对纠错后的解调数据进行编码; 交织器，被配置为交织FEC编码数据并将交错的FEC编码数据输出到后验概率解调器; 以及符号压缩器/解压缩器，被配置为从后验解调器压缩符号数据，并将压缩数据存储在符号存储器中并且被配置为解压缩存储在符号存储器中的压缩符号数据。

公开(公告)号：US10171223B2

公开(公告)日：2019-01-01

申请号：US15867299

申请日：2018-01-10

Applicant: NXP B.V.

Inventor： Artur Tadeusz Burchard ,  Nur Engin

IPC: H04L27/06 ,  H04L5/00 ,  H04B7/022 ,  H04B7/024 ,  H04W84/20 ,  H04B7/08 ,  H04L25/02

Abstract: A wireless receiver for a distributed antenna diversity receiver apparatus comprising a pre-combining component arranged to receive an RF signal from an antenna and to recover and output an information signal contained within the received RF signal, and a combined-signal component arranged to receive the recovered information signal output by the pre-combining component of the wireless receiver and a further recovered information signal from a further wireless receiver and to perform diversity combining of the recovered information signals to obtain and output an enhanced information signal. The wireless receiver further comprises a monitoring component arranged to receive intra-packet channel reliability parameters for the wireless receiver and for the further wireless receiver, determine whether to assign a new master receiver for the distributed antenna diversity receiver apparatus based on the received intra-packet reliability parameters.

公开(公告)号：US20170039104A1

公开(公告)日：2017-02-09

申请号：US14820436

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Nur Engin ,  Steven Thoen ,  Jose Pineda de Gyvez

IPC: G06F11/10 ,  H03M13/35 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/353

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract translation: 根据本发明的一个实施例，公开了一种集成电路（IC）装置。 在该实施例中，IC器件包括SRAM模块，耦合到SRAM模块的封装逻辑，上下文源以及耦合到上下文源和封装逻辑的ECC简档控制器，ECC简档控制器被配置为选择ECC简档 响应于从上下文源接收的用于由包装器逻辑使用的上下文信息。

公开(公告)号：US10223197B2

公开(公告)日：2019-03-05

申请号：US14820436

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Nur Engin ,  Steven Thoen ,  Jose Pineda de Gyvez

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/35

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

公开(公告)号：US10097382B2

公开(公告)日：2018-10-09

申请号：US15841620

申请日：2017-12-14

Applicant: NXP B.V.

Inventor： Semih Serbetli ,  Nur Engin ,  Alessio Filippi

IPC: H04B14/04 ,  H04L25/03 ,  H04L1/00 ,  H04L25/02 ,  H04L25/06 ,  H04L27/227 ,  H04L27/233 ,  H03M13/29

Abstract: A receiver for a modulated signal of a communication system is disclosed. The receiver includes a demodulator to demodulate the received modulated symbols of a received signal into received soft-bits. The receiver also includes a hard-decision decoder that is configured to decode the received soft-bits into decoded bits. A feedback loop is included to provide feedback from the hard decision decoder to the demodulator. The feedback loop is configured to re-encode the decoded bits from the hard-decision decoder into re-encoded bits. The demodulator is further configured to iteratively demodulate the received modulated signal using an output of the feedback loop.

公开(公告)号：US09893920B2

公开(公告)日：2018-02-13

申请号：US15443982

申请日：2017-02-27

Applicant: NXP B.V.

Inventor： Nur Engin ,  Audrey Christine Andrée Cuenin

IPC: H04B3/46 ,  H04L27/26 ,  H04L5/00 ,  H04L25/49

CPC classification number: H04L27/2623 ,  H04L5/0064 ,  H04L25/49 ,  H04L27/2601

Abstract: A signal processing circuit comprising a clip-generation-block. The clip-generation-block is configured to receive an input-signal; and determine a clip-signal that comprises only values of the input-signal that exceed a clipping-threshold. The signal processing circuit also comprises a scaling-block configured to apply a scaling-factor to the clip-signal in order to generate a scaled-clip-signal, wherein the scaling-factor is greater than one; and an adder configured to provide a clipped-signal based on a difference between the scaled-clip-signal and the input signal.

公开(公告)号：US20160050047A1

公开(公告)日：2016-02-18

申请号：US14461030

申请日：2014-08-15

Applicant: NXP B.V.

Inventor： Nur Engin

IPC: H04L1/00

CPC classification number: H04L1/0054 ,  H03M7/00 ,  H03M7/3082 ,  H03M13/2957 ,  H03M13/3776 ,  H03M13/6325 ,  H03M13/6505 ,  H03M13/6588 ,  H04L1/005 ,  H04L1/0071 ,  H04L1/208

Abstract: A receiver, including: a posteriori probability demodulator configured to receive an input digital signal and output demodulated data; a deinterleaver configured to deinterleave the demodulated data; a forward error correction (FEC) decoder configured to error correct the demodulated data; a FEC encoder configured to encode the error corrected demodulated data; an interleaver configured to interleave the FEC encoded data and output the interleaved FEC encoded data to the posteriori probability demodulator; and a symbol compressor/decompressor configured to compress symbol data from the a posteriori demodulator and store the compressed data in a symbol memory and configured to decompress compressed symbol data stored in the symbol memory.

Abstract translation: 一种接收机，包括：后验概率解调器，被配置为接收输入数字信号并输出​​解调数据; 解交织器，被配置为对所解调的数据进行解交织; 配置为纠错解调数据的前向纠错（FEC）解码器; FEC编码器，被配置为对纠错后的解调数据进行编码; 交织器，被配置为交织FEC编码数据并将交错的FEC编码数据输出到后验概率解调器; 以及符号压缩器/解压缩器，被配置为从后验解调器压缩符号数据，并将压缩数据存储在符号存储器中并且被配置为解压缩存储在符号存储器中的压缩符号数据。