公开(公告)号：US10469095B2

公开(公告)日：2019-11-05

申请号：US16119117

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Yu Lin ,  Erwin Janssen ,  Vladislav Dyachenko

IPC: H03M1/38 ,  H03M1/18 ,  G01S13/06 ,  H03M1/10 ,  H03M1/46

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

公开(公告)号：US09584177B2

公开(公告)日：2017-02-28

申请号：US15041217

申请日：2016-02-11

Applicant: NXP B.V.

Inventor： Nenad Pavlovic ,  Vladislav Dyachenko ,  Tarik Saric

IPC: H04L1/00 ,  H04B1/7073 ,  H03L7/197 ,  H04B1/69 ,  H03C3/09

CPC classification number: H04B1/7073 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0991 ,  H03L7/1976 ,  H04B2001/6912 ,  H04B2201/7073

Abstract: A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.

Abstract translation: 公开了一种具有频率控制振荡器，反馈路径，时间到数字转换器和存储器的锁相环。 频率控制振荡器包括用于改变频率控制振荡器的输出频率以跟踪参考频率的第一控制输入和用于调制输出信号的频率以产生啁啾的第二控制输入。 反馈路径被配置为向时间到数字转换器提供输入信号，并且包括调制解除模块，其可操作以从输出信号中去除由第二控制输入产生的频率调制。 存储器存储每个对应于期望啁啾频率并且补偿频率控制振荡器对第二控制输入的响应中的非线性的第二控制输入值。 锁相环可以在啁啾模式下操作，其中通过基于存储器中存储的第二控制输入值确定与期望啁啾频率对应的第二控制输入的值来产生第二控制输入，其中， 锁相环被配置为基于调制消除模块从其中移除由第二控制输入产生的频率调制的反馈路径来确定第一控制输入。