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公开(公告)号：US20200059203A1
公开(公告)日：2020-02-20
申请号：US16522714
申请日：2019-07-26
申请人： NXP USA, INC.
摘要： A circuit (200) for testing failure of a connection between a radio frequency, RF, integrated circuit (201) and external circuitry (204), the circuit comprising: an amplifier (205) having first and second input paths (215, 216) and first and second output paths (206, 207); a first power detector (208, 209) coupled to one of said first or second output paths; at least one connection (211) between said first and second output paths (206, 207) and said external circuitry (204), connecting said outputs to a RF combiner (210) said external circuitry; at least one disabling circuit (230, 232, 234, 236, 240, 242, 260, 262) coupled to at least one of said first and second output paths (206, 207) or at least one of said first and second input path (215, 216), before said path reaches said power detector (208, 209); for disabling one of said inputs or outputs; wherein when said input or output path is disabled (206, 207), and a signal is output along the enabled output path (206, 207), the power detector (208, 209) on said disabled output path can detect if there is a failure in said at least one connection (211).
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12.发明申请公开(公告)号：US20200007309A1
公开(公告)日：2020-01-02
申请号：US16447947
申请日：2019-06-20
申请人： NXP USA, Inc.
摘要： A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).
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公开(公告)号：US20200003882A1
公开(公告)日：2020-01-02
申请号：US16447908
申请日：2019-06-20
申请人： NXP USA, Inc.
发明人： Didier Salle , Cristian Pavao Moreira , Dominique Delbecq , Olivier Doaré , Jean-Stephane Vigier , Birama Goumballa
摘要： A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
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公开(公告)号：US20170307451A1
公开(公告)日：2017-10-26
申请号：US15464145
申请日：2017-03-20
申请人： NXP USA, Inc.
CPC分类号： G01K15/005 , G01K7/01 , G01K7/16 , G05F3/267
摘要： Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.
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公开(公告)号：US20170293265A1
公开(公告)日：2017-10-12
申请号：US15477237
申请日：2017-04-03
申请人： NXP USA, INC.
CPC分类号： G04F10/005 , H03M1/1009
摘要： Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phase alignment.
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公开(公告)号：US11796635B2
公开(公告)日：2023-10-24
申请号：US17391278
申请日：2021-08-02
申请人： NXP USA, INC.
CPC分类号： G01S7/4008 , G01S7/4021 , G01S13/26 , H03H11/16
摘要： The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver (200) having a normal mode of transmitter operation and a self-test mode of operation, the transceiver (200) comprising: a digital controller (116) configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter (122) configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter (124) configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load (240) connected to receive the analogue signal from the digital to analogue converter (122) and to provide an analogue output; a resistor network (331) connected across an output of the dummy load (240); a testing module (335) configured to measure the analogue output of the dummy load (240); and a controller module (339) configured to control operation of the dummy load (240), testing module (335) and digital controller (116) during the self-test mode of operation by: enabling the dummy load (240); operating the digital controller (116) to provide a range of digital control signals to the digital to analogue converter (122); and operate the testing module (335) to measure the analogue output of the dummy load (240) to determine a measure of linearity of the digital to analogue converter (122).
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公开(公告)号：US11054513B2
公开(公告)日：2021-07-06
申请号：US16447962
申请日：2019-06-21
申请人： NXP USA, Inc.
发明人： Olivier Doaré , Didier Salle , Cristian Pavao Moreira , Julien Orlando , Jean-Stephane Vigier , Andres Barrilado Gonzalez
IPC分类号： G01S13/34 , G01S7/35 , G01S7/40 , G01S13/931
摘要： A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784). The at least one master device (710) and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed system clock signal (784) and re-create therefrom a synchronized system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the the master device (710) and at least one slave device (720).
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公开(公告)号：US10763864B2
公开(公告)日：2020-09-01
申请号：US16145782
申请日：2018-09-28
申请人： NXP USA, INC.
摘要： The disclosure relates to voltage-controlled-oscillator circuit comprising: a charge-pump configured to generate a tuning-voltage, the tuning-voltage having a minimum-operating-voltage; an offset-voltage-source configured to generate an offset-voltage in accordance with the minimum-operating-voltage; and a voltage-controlled-oscillator, VCO, configured to provide an oscillator frequency in accordance with the tuning-voltage and the offset-voltage.
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公开(公告)号：US10700672B2
公开(公告)日：2020-06-30
申请号：US16591758
申请日：2019-10-03
申请人： NXP USA, Inc.
摘要： An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal.
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公开(公告)号：US20200057140A1
公开(公告)日：2020-02-20
申请号：US15999181
申请日：2018-08-17
申请人： NXP USA, Inc.
摘要： A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.
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