公开(公告)号：US10826431B2

公开(公告)日：2020-11-03

申请号：US16427455

申请日：2019-05-31

申请人： NXP USA, INC.

发明人： Yi Yin ,  Baptiste Barroué ,  Birama Goumballa

IPC分类号： H03B5/12

摘要： The present application relates to a differential Colpitts voltage-controlled oscillator (VCO) circuit, which comprises a pair of transistors with control terminals biased by a common biasing voltage and a pair of couplers arranged to cross-couple corrector/drain of the transistors and the base/gate of the differential transistors. The pair of couplers have a coupling factor kc, which used to enhance the transconductance of the transistor pair, therefore can be used for power consumption reduction and phase noise minimalization.

公开(公告)号：US10648870B2

公开(公告)日：2020-05-12

申请号：US15464145

申请日：2017-03-20

申请人： NXP USA, Inc.

发明人： Birama Goumballa ,  Didier Salle ,  Olivier Doare ,  Cristian Pavao Moreira

IPC分类号： G01K15/00 ,  G01K7/01 ,  G01K7/16 ,  G05F3/26

摘要： Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.

公开(公告)号：US10381051B2

公开(公告)日：2019-08-13

申请号：US15616125

申请日：2017-06-07

申请人： NXP USA, Inc.

发明人： Birama Goumballa ,  Cristian Pavao Moreira ,  Pierre Pascal Savary

IPC分类号： G11C5/14 ,  G05F1/10 ,  H03L7/089 ,  H02M3/07 ,  H03K3/03 ,  H02M1/00

摘要： A charge pump driver circuit (320) arranged to output a charge pump control signal (325). The charge pump driver circuit (320) includes a bias current source component (330) arranged to generate a bias current (335), a control stage (340) and an output stage (350). The control stage (340) is coupled to the bias current source component (330) and arranged to receive the bias current (335). The control stage (340) is further arranged to receive an input signal (215) and to generate a control current signal (345) proportional to the bias current (335) in accordance with the input signal (215). The output stage (350) is arranged to receive the control current signal (345) generated by the control stage (340) and to generate the charge pump control voltage signal (325) based on the control current signal (345) generated by the control stage (340). The bias current source component (330) is arranged to vary the bias current (335) in response to variations in temperature.

公开(公告)号：US10211840B2

公开(公告)日：2019-02-19

申请号：US15410890

申请日：2017-01-20

申请人： NXP USA, Inc.

发明人： Pierre Pascal Savary ,  Dominique Delbecq ,  Birama Goumballa

IPC分类号： H03L7/089 ,  H03L7/183

摘要： A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.

公开(公告)号：US10097187B2

公开(公告)日：2018-10-09

申请号：US15710154

申请日：2017-09-20

申请人： NXP USA, Inc.

发明人： Olivier Vincent Doare ,  Didier Salle ,  Birama Goumballa ,  Cristian Pavao Moreira

IPC分类号： H03L7/099 ,  H03L7/091 ,  H03L1/00 ,  H03L7/095 ,  G01S7/35

摘要： A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal. A digital synthesizer circuit sensor is configured to sense an operational condition of the digital synthesizer circuit and select one of the multiple selectable delays output from the TDC in response to the sensed operational condition. A re-timer circuit is coupled to the digital synthesizer circuit sensor and configured to synchronize the selected delayed DCO output signal with the reference frequency signal.

公开(公告)号：US11796635B2

公开(公告)日：2023-10-24

申请号：US17391278

申请日：2021-08-02

申请人： NXP USA, INC.

发明人： Birama Goumballa ,  Gilles Montoriol ,  Cristian Pavao Moreira ,  Dominique Delbecq

IPC分类号： G01S7/40 ,  G01S13/26 ,  H03H11/16

CPC分类号： G01S7/4008 ,  G01S7/4021 ,  G01S13/26 ,  H03H11/16

摘要： The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver (200) having a normal mode of transmitter operation and a self-test mode of operation, the transceiver (200) comprising: a digital controller (116) configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter (122) configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter (124) configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load (240) connected to receive the analogue signal from the digital to analogue converter (122) and to provide an analogue output; a resistor network (331) connected across an output of the dummy load (240); a testing module (335) configured to measure the analogue output of the dummy load (240); and a controller module (339) configured to control operation of the dummy load (240), testing module (335) and digital controller (116) during the self-test mode of operation by: enabling the dummy load (240); operating the digital controller (116) to provide a range of digital control signals to the digital to analogue converter (122); and operate the testing module (335) to measure the analogue output of the dummy load (240) to determine a measure of linearity of the digital to analogue converter (122).

公开(公告)号：US20220196791A1

公开(公告)日：2022-06-23

申请号：US17451828

申请日：2021-10-22

申请人： NXP USA, INC.

发明人： Olivier Vincent Doaré ,  Birama Goumballa

IPC分类号： G01S7/02

摘要： There is described a method of determining phase error caused by impairments in a phase rotator, said impairments including leakage in mixers and/or multipliers of the phase rotator, gain/amplitude imbalance and a known phase imbalance between an I path and a Q path in the phase rotator, the phase rotator having an input for receiving a reference phase value, a local oscillator and circuitry configured to provide an output signal with a phase corresponding to the reference phase value. The method comprises (a) forcing the Q path of the phase rotator to zero and obtaining a first sequence of successive measurement values indicative of a power of the phase rotator output signal, each successive measurement value in the first sequence corresponding to one of a plurality of successive reference phase values, (b) forcing the I path of the phase rotator to zero and obtaining a second sequence of successive measurement values indicative of the power of the phase rotator output signal, each successive measurement value in the second sequence corresponding to one of the plurality of successive reference phase values, (c) forming a sequence of successive measurement value pairs, each measurement value pair comprising one measurement value from the first sequence of successive measurement values and one measurement value from the second sequence of successive measurement values, wherein the first sequence of successive measurement values is shifted relative to the second sequence of successive measurement values by an amount corresponding to the known phase imbalance, (d) calculating an actual phase value for each of the successive measurement value pairs, and (e) determining the phase error by comparing the actual phase values with the corresponding reference phase values. Furthermore, a corresponding device and a radar system comprising such a device are described.

公开(公告)号：US10763864B2

公开(公告)日：2020-09-01

申请号：US16145782

申请日：2018-09-28

申请人： NXP USA, INC.

发明人： Birama Goumballa ,  Pierre Savary ,  Cristian Pavao Moreira

IPC分类号： H03L1/02 ,  G01S7/03 ,  H03L7/099 ,  H03L7/089

摘要： The disclosure relates to voltage-controlled-oscillator circuit comprising: a charge-pump configured to generate a tuning-voltage, the tuning-voltage having a minimum-operating-voltage; an offset-voltage-source configured to generate an offset-voltage in accordance with the minimum-operating-voltage; and a voltage-controlled-oscillator, VCO, configured to provide an oscillator frequency in accordance with the tuning-voltage and the offset-voltage.

公开(公告)号：US20200007310A1

公开(公告)日：2020-01-02

申请号：US16447979

申请日：2019-06-21

申请人： NXP USA, Inc.

发明人： Cristian Pavao Moreira ,  Birama Goumballa ,  Jean-Stephane Vigier ,  Matthis Bouchayer

IPC分类号： H04L7/06 ,  H04L7/00

摘要： A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one of at least one master device and at least one slave device comprises a demodulator circuit (564, 565) configured to: receive a modulated embedded master-slave clock signal (584) that comprises a system clock signal (582) with an embedded frame start signal (580); demodulate the modulated embedded master-slave clock signal (584); and re-create therefrom the system clock signal (588, 585) and the frame start signal (590, 586).

公开(公告)号：US10236898B2

公开(公告)日：2019-03-19

申请号：US15660649

申请日：2017-07-26

申请人： NXP USA, Inc.

发明人： Didier Salle ,  Olivier Vincent Doare ,  Birama Goumballa ,  Cristian Pavao Moreira

IPC分类号： H03L7/06 ,  H03L7/099 ,  H03K4/06 ,  H03L7/085 ,  G01S13/34 ,  H03C3/09 ,  H03L7/08 ,  H03L7/093 ,  H03L7/16 ,  G01S7/35

摘要： A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.