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公开(公告)号：US20200136599A1
公开(公告)日：2020-04-30
申请号：US16591758
申请日：2019-10-03
申请人： NXP USA, Inc.
摘要： An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal.
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公开(公告)号：US20200057138A1
公开(公告)日：2020-02-20
申请号：US16410013
申请日：2019-05-13
申请人： NXP USA, INC.
摘要： A radar device (100) is described that includes at least one transceiver (105) configured to support frequency modulated continuous wave (FMCW); radar device (100) and a digital controller (262). A temperature sensor system includes a plurality of temperature sensors (222, 232, 242) coupled to one or more circuits (220, 230, 240) in the at least one transceiver (105). The digital controller (262, 306) comprises or is operably coupled to an over-temperature emulation circuit (308) configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal (290) into the temperature sensor system (270).
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公开(公告)号：US12038528B2
公开(公告)日：2024-07-16
申请号：US17459007
申请日：2021-08-27
申请人： NXP USA, INC.
IPC分类号： G01S7/35 , G01S7/03 , G01S13/931
CPC分类号： G01S7/352 , G01S7/032 , G01S13/931
摘要： In accordance with a first aspect of the present disclosure, a radar unit is provided, comprising: a receiver circuit configured to receive a radar signal; a controller configured to control said receiver circuit, wherein said controller is configured to cause said receiver circuit to operate either in a complex receiver mode or in a real receiver mode. In accordance with a second aspect of the present disclosure, a method of operating a radar unit is conceived, comprising: receiving, by a receiver circuit comprised in the radar unit, a radar signal; controlling, by a controller comprised in said radar unit, said receiver circuit, wherein said controller causes said receiver circuit to operate either in a complex receiver mode or in a real receiver mode.
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公开(公告)号：US11815553B2
公开(公告)日：2023-11-14
申请号：US17336843
申请日：2021-06-02
申请人： NXP USA, INC.
IPC分类号： G01R31/317 , G01S7/40 , H03K3/017
CPC分类号： G01R31/31727 , G01S7/4008 , G01S7/4021 , H03K3/017
摘要： The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).
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公开(公告)号：US10992304B2
公开(公告)日：2021-04-27
申请号：US16875526
申请日：2020-05-15
申请人： NXP USA, INC.
摘要： An example apparatus (100) is for use for use with front-end circuitry (102) to transmit and receive radar wave signals, The apparatus (100) includes digital phase locked loop (PLL) circuitry (104) and a control circuit (106). The digital PLL circuitry (106) provides a chirp sequence with frequency modulated continuous wave signals (FMCW), the FMCW signals being chirps containing a start frequency and a stop frequency, representing a selected chirp bandwidth (BW). The digital PLL circuitry (104) includes the DCO circuit (108) which frequency resolution is configured and arranged to be tuned relative to the selected chirp BW, the frequency resolution configured in response to a selected level of capacitance. The control circuit (106) controls the selected level of capacitance used by the DCO circuit (108) by changing the frequency resolution of the DCO according to the selected chirp BW, wherein different frequency resolutions are used for a first selected chirp BW and for a second selected chirp BW.
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公开(公告)号：US10648870B2
公开(公告)日：2020-05-12
申请号：US15464145
申请日：2017-03-20
申请人： NXP USA, Inc.
摘要： Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.
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公开(公告)号：US10381051B2
公开(公告)日：2019-08-13
申请号：US15616125
申请日：2017-06-07
申请人： NXP USA, Inc.
摘要： A charge pump driver circuit (320) arranged to output a charge pump control signal (325). The charge pump driver circuit (320) includes a bias current source component (330) arranged to generate a bias current (335), a control stage (340) and an output stage (350). The control stage (340) is coupled to the bias current source component (330) and arranged to receive the bias current (335). The control stage (340) is further arranged to receive an input signal (215) and to generate a control current signal (345) proportional to the bias current (335) in accordance with the input signal (215). The output stage (350) is arranged to receive the control current signal (345) generated by the control stage (340) and to generate the charge pump control voltage signal (325) based on the control current signal (345) generated by the control stage (340). The bias current source component (330) is arranged to vary the bias current (335) in response to variations in temperature.
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公开(公告)号：US10097187B2
公开(公告)日：2018-10-09
申请号：US15710154
申请日：2017-09-20
申请人： NXP USA, Inc.
摘要： A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal. A digital synthesizer circuit sensor is configured to sense an operational condition of the digital synthesizer circuit and select one of the multiple selectable delays output from the TDC in response to the sensed operational condition. A re-timer circuit is coupled to the digital synthesizer circuit sensor and configured to synchronize the selected delayed DCO output signal with the reference frequency signal.
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公开(公告)号：US20180123536A1
公开(公告)日：2018-05-03
申请号：US15798961
申请日：2017-10-31
申请人： NXP USA, Inc.
CPC分类号： H03F3/45089 , G01S7/02 , H03F1/0261 , H03F3/195 , H03F3/26 , H03F3/45
摘要： A baseband amplifier circuit comprising a single-ended to differential converter followed by at least one boosted follower amplifier. The boosted follower amplifier comprises a first transconductance device arranged to control a first current between a first supply node and a first output node in response to a voltage at a first input node, a second transconductance device arranged to control a second current between the first output node and a second supply node in response to a voltage at a second input node, a third transconductance device arranged to control a third current between the first supply node and a second output node in response to a voltage at a third input node, and a fourth transconductance device arranged to control a fourth current between the second output node of the boosted follower amplifier and the second supply node in response to a voltage at a fourth input node.
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公开(公告)号：US10579021B2
公开(公告)日：2020-03-03
申请号：US15599571
申请日：2017-05-19
申请人： NXP USA, INC.
摘要： A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.
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