公开(公告)号：US07724075B2

公开(公告)日：2010-05-25

申请号：US11634776

申请日：2006-12-06

申请人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

发明人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

IPC分类号： G05F1/575

CPC分类号： G11C5/147 ,  G05F3/08 ,  G11C16/30

摘要： A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith. The comparator circuit is configured to compare the bias supply voltage to the reference voltage, and drive the bias supply and the variable divider circuit in response to the comparison, thereby quickly stabilizing the reference voltage.

摘要翻译： 具有有源反馈的快速参考电路包括偏置电源电路和通过有源反馈路径连接到偏置电源电路的可变分频器电路，以及连接到可变分频器电路，偏置电源电路和参考节点的参考节点 可变分频电路。 在一个实施例中，启动电路首先在偏置电源和比较器电路处放电，然后在约零伏特的参考节点初始化参考电压，以提高可重复性。 在一个实施例中，可变分压器包括基于用于制造快速参考电路的工艺的薄层电阻而修整的阻抗，并且还包括耦合到阻抗的可变参考电流电路，并且被配置为产生具有 基于所需参考电压的值，并且将电流传导通过阻抗，由此产生与其相关联的参考电压。 比较器电路被配置为将偏置电源电压与参考电压进行比较，并且响应于比较来驱动偏置电源和可变分频器电路，由此快速稳定参考电压。

公开(公告)号：US20090147587A1

公开(公告)日：2009-06-11

申请号：US11951262

申请日：2007-12-05

申请人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

发明人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

IPC分类号： G11C16/00

CPC分类号： G11C16/30 ,  G11C7/12 ,  G11C16/24

摘要： Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.

摘要翻译： 通常，存储线的读取时间由于电压过冲和/或电压下冲而变慢。 为了消除这些问题，控制部件可以管理电压，同时泄漏部件管理电压的时序。 这允许产生增加读取时间的线路预充电。 控制组件可以实现一个可变电阻器来修改值来补偿温度。 泄漏部件可以包括允许电压通过的电容器配置。

公开(公告)号：US07460415B2

公开(公告)日：2008-12-02

申请号：US11639936

申请日：2006-12-15

申请人： Yonggang Wu ,  Nian Yang ,  Tien-Chun Yang

发明人： Yonggang Wu ,  Nian Yang ,  Tien-Chun Yang

IPC分类号： G11C5/14

CPC分类号： G11C7/16 ,  G11C5/147 ,  G11C7/12

摘要： A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

摘要翻译： 电压调节器包括减轻编程电压（VPROG）变化的电阻元件。 特别地，电阻允许电压调节器的副本在半导体衬底上更一致地制造。 因此，减轻了施加到存储器装置的不同位线的各个编程电压的变化。 随着越来越多的设备按需要执行，这减轻了产量损失，因此需要更少的丢弃物。

公开(公告)号：US07345916B2

公开(公告)日：2008-03-18

申请号：US11423638

申请日：2006-06-12

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US20070291550A1

公开(公告)日：2007-12-20

申请号：US11423638

申请日：2006-06-12

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C8/00 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US07746706B2

公开(公告)日：2010-06-29

申请号：US11639935

申请日：2006-12-15

申请人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

发明人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

IPC分类号： G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.

摘要翻译： 本发明的一个实施例涉及访问存储器单元的方法。 在该方法中，擦除存储单元的至少一位。 在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。 还公开了其它方法和系统。

公开(公告)号：US07613044B2

公开(公告)日：2009-11-03

申请号：US11950811

申请日：2007-12-05

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/10

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

摘要翻译： 提供了一种用于在半导体存储器件（100）的选定存储单元（200）上进行高性能，高电压存储器操作的方法和装置。 在编程或擦除操作期间，高电压发生器（106）在所选择的字线（502）上提供连续的高电压电平（702），并且向位线解码器（120）保持连续的高电压电平供应，位线解码器（120）依次提供高电压 电平（706）到位线（504）的第一部分，并且在将高电压电平提供给第二部分（710）之前对那些位线（504）进行放电（708）。 为了对编程操作进一步改进，高电压发生器（106）通过在其间提供电流控制装置（1208）来解耦提供给字线（502）和位线（504）的高电压，并在 时间（1104）以克服由与所选位线（504）和/或位线解码器（120）相关联的电容器负载导致的电压电平下降（1102），所述位线（504）的第二部分预充电（1716） 同时向第一部分提供高电压电平以对存储单元（200）的第一部分进行编程（1706）。 为了改进读取操作，动态参考单元（2002）是空白的是通过从第一电压源（2112）到动态参考单元（2002）和从第二电压源（2104）提供非相同调节的高电压电平来确定的 ）到静态参考单元（2004），并且如果动态参考单元（2002）不为空白，则通过向所选择的存储单元（200），动态参考单元（200）提供相同调节的高电压电平来读取所选存储单元（200） 2002）和静态参考单元（2004）。

公开(公告)号：US20080144391A1

公开(公告)日：2008-06-19

申请号：US11639935

申请日：2006-12-15

申请人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

发明人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

IPC分类号： G11C16/10

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.

摘要翻译： 本发明的一个实施例涉及访问存储器单元的方法。 在该方法中，擦除存储单元的至少一位。 在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。 还公开了其它方法和系统。

公开(公告)号：US20070284609A1

公开(公告)日：2007-12-13

申请号：US11423649

申请日：2006-06-12

申请人： Boon-Aik Ang ,  Nian Yang ,  Yonggang Wu

发明人： Boon-Aik Ang ,  Nian Yang ,  Yonggang Wu

IPC分类号： H01L29/74

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/07

摘要： A method and apparatus are provided for improved power conservation in a semiconductor device (100) which includes a high voltage generating circuit (200) such as a drain pump. The operation frequency of the drain pump (200) is controlled in response to the high voltage level detected at the output thereof. In addition, highly efficient operation of the drain pump (200) can be achieved by enabling and disabling the drain pump (200) in response to the high voltage level to provide an output signal at a relatively constant high voltage level. The drain pump (200) is enabled in response to a high voltage detector (202, 402, 502) detecting a high voltage level lower than a first predetermined voltage level and is disabled in response to detecting a voltage level higher than a second predetermined voltage level, the second predetermined voltage level being higher than the first predetermined voltage level.

摘要翻译： 提供了一种用于在包括诸如排水泵的高电压产生电路（200）的半导体器件（100）中改善功率节省的方法和装置。 排水泵（200）的运转频率根据其输出端检测到的高电压电平进行控制。 此外，可以通过响应于高电压电平启用和禁用排水泵（200）来实现排水泵（200）的高效率操作，以在相对恒定的高电压电平提供输出信号。 响应于检测到低于第一预定电压电平的高电压电平的高电压检测器（202,402,502）响应于检测到高于第二预定电压的电压电平而禁用排水泵（200） 电平，第二预定电压电平高于第一预定电压电平。

公开(公告)号：US07749855B2

公开(公告)日：2010-07-06

申请号：US11838483

申请日：2007-08-14

申请人： Nian Yang ,  Yonggang Wu ,  David Aoyagi

发明人： Nian Yang ,  Yonggang Wu ,  David Aoyagi

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/7923

摘要： A method of forming a capacitor for use as a charge pump with flash memory, comprising: (a) concurrently forming polysilicon gates on a semiconductor body in a core region and a polysilicon middle capacitor plate in a peripheral region, (b) forming a first dielectric layer over the polysilicon gates and the middle capacitor plate, (c) planarizing the first dielectric layer to expose a top portion of the polysilicon gates and a top portion of the middle capacitor plate, (d) forming a second dielectric layer over the top portion of the middle capacitor layer, (e) concurrently forming patterning a second polysilicon layer in the core region and a third capacitor plate in the periphery region and (f) connecting the third capacitor plate to the source/drain well.

摘要翻译： 一种形成用作具有闪速存储器的电荷泵的电容器的方法，包括：（a）在芯区域中的半导体本体和外围区域中的多晶硅中间电容器板同时形成多晶硅栅极，（b）形成第一 在多晶硅栅极和中间电容器板上的电介质层，（c）平坦化第一介电层以暴露多晶硅栅极的顶部和中间电容器板的顶部，（d）在顶部上形成第二电介质层 （e）同时形成芯区域中的第二多晶硅层图案和周边区域中的第三电容器板，以及（f）将第三电容器板连接到源极/漏极阱。