利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

253 条记录 (耗时 0.031 秒)

    SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090302293A1

    公开(公告)日：2009-12-10

    申请号：US12094403

    申请日：2006-11-14

    申请人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    发明人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    IPC分类号： H01L27/105 ,  H01L45/00

    CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

    摘要翻译： 在相同的半导体衬底1上，存储单元阵列，其中具有存储具有高电阻值的高电阻状态的硫族化物材料存储层22的多个存储元件R和具有低电阻的低电阻状态 在存储单元区域mmry中形成以矩阵形式设置的原子排列变化的值，在逻辑电路区域lgc中形成半导体集成电路。 该硫属化物材料储存层22由含有10.5原子％以上至40原子％以下的Ga或In中的至少任一种的硫属元素化物构成，5原子％以上且35原子％以下的Ge，Sb 为5原子％以上且25原子％以下，Te为40原子％以上且65原子％以下。

    Semiconductor device
    12.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08513640B2

    公开(公告)日：2013-08-20

    申请号：US12094403

    申请日：2006-11-14

    申请人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    发明人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    IPC分类号： H01L29/06 ,  H01L21/00

    CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

    摘要翻译： 在相同的半导体衬底1上，存储单元阵列，其中具有存储具有高电阻值的高电阻状态的硫族化物材料存储层22的多个存储元件R和具有低电阻的低电阻状态 在存储单元区域mmry中形成以矩阵形式设置的原子排列变化的值，在逻辑电路区域lgc中形成半导体集成电路。 该硫属化物材料储存层22由含有10.5原子％以上至40原子％以下的Ga或In中的至少任一种的硫属元素化物构成，5原子％以上且35原子％以下的Ge，Sb 为5原子％以上且25原子％以下，Te为40原子％以上且65原子％以下。

    SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME
    13.
    发明申请
    SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20100171087A1

    公开(公告)日：2010-07-08

    申请号：US12600333

    申请日：2007-05-21

    申请人： Kenzo Kurotsuchi ,  Motoyasu Terao ,  Takahiro Morikawa ,  Norikatsu Takaura

    发明人： Kenzo Kurotsuchi ,  Motoyasu Terao ,  Takahiro Morikawa ,  Norikatsu Takaura

    IPC分类号： H01L45/00 ,  H01L21/06

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： In a semiconductor device including a phase change memory element whose memory layer is formed of a phase change material of M (additive element)-Ge (germanium)-Sb (antimony)-Te (tellurium), both of high heat resistance and stable data retention property are achieved. The memory layer has a fine structure with a different composition ratio therein, and an average composition of MαGeXSbYTeZ forming the memory layer satisfies the relations of 0≦α≦0.4, 0.04≦X≦0.4, 0≦Y≦0.3, 0.3≦Z≦0.6, and 0.03≦(α+Y).

    摘要翻译： 在包括由M（添加元素）-Ge（锗）-Sb（锑）-Te（碲）的相变材料形成的存储层的相变存储元件的半导体器件中，高耐热性和稳定数据 保留性能得以实现。 存储层具有不同组成比的精细结构，形成记忆层的MαGeXSbYTeZ的平均组成满足0＆lt; nlE;α＆nlE; 0.4,0.04＆nlE; X＆lt; lE; 0.4,0＆amp; nlE; Y＆nlE; 0.3,0.3＆ Z＆NlE; 0.6和0.03＆nlE;（α+ Y）。

    Semiconductor and semiconductor manufacturing arrangements having a chalcogenide layer formed of columnar crystal grains perpendicular to a main substrate surface
    14.
    发明授权
    Semiconductor and semiconductor manufacturing arrangements having a chalcogenide layer formed of columnar crystal grains perpendicular to a main substrate surface 有权
    具有由垂直于主衬底表面的柱状晶粒形成的硫族化物层的半导体和半导体制造布置

    公开(公告)号：US07638786B2

    公开(公告)日：2009-12-29

    申请号：US11272811

    申请日：2005-11-15

    申请人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    发明人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    IPC分类号： H01L29/02

    CPC分类号： C23C14/5806 ,  C23C14/0623 ,  C23C14/541 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

    摘要： The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

    摘要翻译： 在相变存储器的布线处理所需的400℃以上所需的退火处理的问题在于，硫属化物材料中的晶粒沿倾斜方向生长，从而在储存层中产生空隙。 这些空隙又由于粘合力的降低而导致剥离，由于与插头的不正确接触导致的电阻变化以及其它不期望的事件。 在非晶态形成硫族化物材料之后，进行后退火以形成（111）取向和柱状结构的面心立方。 此后进一步进行高温退火以形成柱状，六边形最接近填充的晶体。 使用该方法可以抑制由于在垂直于相关衬底的表面的方向上形成晶粒而导致空隙的倾斜晶粒的生长。

    Semiconductor device and method of manufacturing the same
    15.
    发明申请
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20060105556A1

    公开(公告)日：2006-05-18

    申请号：US11272811

    申请日：2005-11-15

    申请人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    发明人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    IPC分类号： H01L21/20

    CPC分类号： C23C14/5806 ,  C23C14/0623 ,  C23C14/541 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

    摘要： The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

    摘要翻译： 在相变存储器的布线处理所需的400℃以上所需的退火处理的问题在于，硫属化物材料中的晶粒沿倾斜方向生长，从而在储存层中产生空隙。 这些空隙又由于粘合力的降低而导致剥离，由于与插头的不正确接触导致的电阻变化以及其它不期望的事件。 在非晶态形成硫族化物材料之后，进行后退火以形成（111）取向和柱状结构的面心立方。 此后进一步进行高温退火以形成柱状，六边形最接近填充的晶体。 使用该方法可以抑制由于在垂直于相关衬底的表面的方向上形成晶粒而导致空隙的倾斜晶粒的生长。

    Semiconductor integrated circuit device
    16.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08129707B2

    公开(公告)日：2012-03-06

    申请号：US12487492

    申请日：2009-06-18

    申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Kenzo Kurotsuchi ,  Tsuyoshi Yamauchi

    发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Kenzo Kurotsuchi ,  Tsuyoshi Yamauchi

    IPC分类号： H01L47/00

    CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

    摘要翻译： 通过高速非易失性相变存储器，提高了刷新次数的可靠性。 在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中，形成了使用相变材料的包括电阻元件的存储单元的相变材料层，用于常用。 结果，减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化，从而提高了存储单元的刷新次数的可靠性。