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公开(公告)号:US20060274593A1
公开(公告)日:2006-12-07
申请号:US11501118
申请日:2006-08-09
申请人: Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人: Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号: G11C17/18
CPC分类号: G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要: In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
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公开(公告)号:US07123535B2
公开(公告)日:2006-10-17
申请号:US11002245
申请日:2004-12-03
申请人: Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人: Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号: G11C17/18
CPC分类号: G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要: In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
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公开(公告)号:US07489552B2
公开(公告)日:2009-02-10
申请号:US11501118
申请日:2006-08-09
申请人: Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人: Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号: G11C11/34
CPC分类号: G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要: In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
摘要翻译: 在非易失性相变存储器中,利用相变部分的电阻变化来记录信息。 当相变部分产生焦耳热并保持在特定温度时,其进入低电阻状态。 当控制存储单元选择晶体管QM的栅极电压以提供低电阻状态时,通过向控制栅极施加中等电压来限制施加到相变部分的最大电流量,从而避免过热 的相变部。
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公开(公告)号:US20050128799A1
公开(公告)日:2005-06-16
申请号:US11002245
申请日:2004-12-03
CPC分类号: G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要: In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. At this time, if a constant voltage source is used, not only the phase change portion assumes a state of a low resistance, but also a large current flows, so that a sample concerned is overheated and goes into a state of a high resistance. Thus, it is difficult to make the phase change portion low in resistance stably. When the gate voltage of a memory cell selection transistor QM is controlled with MISFET to afford a low resistance state, the maximum amount of current applied to the sample is limited by the application of a medium-state voltage.
摘要翻译: 在非易失性相变存储器中,利用相变部分的电阻变化来记录信息。 当相变部分产生焦耳热并保持在特定温度时,其进入低电阻状态。 此时,如果使用恒定电压源,则不仅相变部分呈现低电阻状态,而且流过大电流,使得有关样品过热并进入高电阻状态。 因此,难以稳定地使相位变化部的电阻低。 当用MISFET控制存储单元选择晶体管QM的栅极电压以提供低电阻状态时,施加到样品的最大电流量受到施加中等电压的限制。
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公开(公告)号:US08319204B2
公开(公告)日:2012-11-27
申请号:US12373185
申请日:2006-07-21
申请人: Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
发明人: Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
CPC分类号: G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.
摘要翻译: 作为存储单元区域中的存储元件RM,使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52, 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如,记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子%以上。 此外,提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。
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公开(公告)号:US20090039336A1
公开(公告)日:2009-02-12
申请号:US12176606
申请日:2008-07-21
申请人: Motoyasu Terao , Yoshitaka Sasago , Kenzo Kurotsuchi , Kazuo Ono , Yoshihisa Fujisaki , Norikatsu Takaura , Riichiro Takemura
发明人: Motoyasu Terao , Yoshitaka Sasago , Kenzo Kurotsuchi , Kazuo Ono , Yoshihisa Fujisaki , Norikatsu Takaura , Riichiro Takemura
IPC分类号: H01L45/00
CPC分类号: G11C11/5614 , G11C13/0011 , G11C13/0069 , G11C2013/0083 , G11C2213/11 , G11C2213/15 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/1675
摘要: The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen.
摘要翻译: 提高了能够存储信息的半导体装置的性能。 存储元件的存储层由底部电极侧的第一层和顶部电极侧的第二层形成。 第一层含有20-70原子%的Cu,Ag,Au,Al,Zn和Cd的第一元素基团的至少一种元素,含有3-40原子%的至少一种元素的第二元素基团 V,Nb,Ta,Cr,Mo,W,Ti,Zr,Hf,Fe,Co,Ni,Pt,Pd,Rh,Ir,Ru,Os和镧系元素,至少含有20-60原子% S,Se和Te的第三要素组的一个元素。 第二层含有5-50原子%的第一元素基团的至少一个元素,10-50原子%的第二元素基团的至少一个元素和30-70原子%的氧。
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公开(公告)号:US20090039335A1
公开(公告)日:2009-02-12
申请号:US12162769
申请日:2006-02-09
IPC分类号: H01L45/00
CPC分类号: H01L27/101 , G11C13/0004 , G11C13/0011 , G11C2213/79 , H01L27/0688 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要: On an insulating film (31) in which a plug (35) is embedded, a second component releasing region (45) made of a first component and a second component, a solid electrolyte region (46) made of chalcogenide and an upper electrode region (47) are sequentially formed. The second component releasing region (45) made of a first component and a second component is composed of dome-shaped electrode portions (43) and an insulating film (44) burying the peripheries of the electrode portions (43), and at least one electrode portion (43) exists on the plug (34). The electrode portion (43) is composed of a first portion made of the first component such as tantalum oxide that is stable even when electric field is applied thereto and a second portion made of the second component such as copper or silver that is easily diffused in the solid electrolyte region (42) and moves therein by the application of an electric field. The second component supplied from the electrode portion (43) moves in the solid electrolyte region (46), thereby storing the information.
摘要翻译: 在其中嵌入有插塞(35)的绝缘膜(31)上,由第一部件和第二部件制成的第二部件释放区域(45),由硫族化物制成的固体电解质区域(46)和上部电极区域 (47)。 由第一部件和第二部件制成的第二部件释放区域(45)由埋入电极部分(43)的周边的圆顶状电极部分(43)和绝缘膜(44)组成,并且至少一个 电极部分(43)存在于插头(34)上。 电极部(43)由第一部分(例如氧化钽)构成的第一部分,即使施加电场也是稳定的,而由诸如铜或银的第二部分制成的第二部分容易扩散 固体电解质区域(42)并通过施加电场而在其中移动。 从电极部(43)供给的第二部件在固体电解质区域(46)中移动,从而存储信息。
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公开(公告)号:US20100072451A1
公开(公告)日:2010-03-25
申请号:US12373185
申请日:2006-07-21
申请人: Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
发明人: Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
CPC分类号: G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.
摘要翻译: 作为存储单元区域中的存储元件RM,使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52, 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如,记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子%以上。 此外,提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。
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公开(公告)号:US08129707B2
公开(公告)日:2012-03-06
申请号:US12487492
申请日:2009-06-18
IPC分类号: H01L47/00
CPC分类号: H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.
摘要翻译: 通过高速非易失性相变存储器,提高了刷新次数的可靠性。 在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中,形成了使用相变材料的包括电阻元件的存储单元的相变材料层,用于常用。 结果,减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化,从而提高了存储单元的刷新次数的可靠性。
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公开(公告)号:US07834337B2
公开(公告)日:2010-11-16
申请号:US10587079
申请日:2004-12-20
IPC分类号: H01L29/02
CPC分类号: G11C13/0004 , G11C13/04 , G11C13/047 , G11C2213/56 , G11C2213/71 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1625
摘要: A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145° C. or higher.The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40 at % or more and 65 at % or less in Zn-Ge-Te.
摘要翻译: 包括具有存储元件和选择晶体管的存储单元的相变存储器件的耐热性得到改善,使得其在145℃以上可操作。 使用具有20原子%以上且50原子%以下的Zn或Cd含量的记忆层,Ge或Sb的含量为5原子%以上且25原子%以下,Te含量 在Zn-Ge-Te中为40at%以上且65at%以下。
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