公开(公告)号：US20240397236A1

公开(公告)日：2024-11-28

申请号：US18322408

申请日：2023-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Jiayu Guo ,  Liang Zuo ,  Lihang Fan

IPC: H04N25/78 ,  H04N25/616

Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

公开(公告)号：US11632512B2

公开(公告)日：2023-04-18

申请号：US17180520

申请日：2021-02-19

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Min Qu ,  Chao-Fang Tsai ,  Chun-Hsiang Chang

IPC: H04N5/378 ,  H03M1/12 ,  G06F7/575 ,  G06F7/507 ,  H03M1/28

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

公开(公告)号：US11431936B2

公开(公告)日：2022-08-30

申请号：US16854765

申请日：2020-04-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Min Qu ,  Yu-Shen Yang ,  Charles Qingle Wu

IPC: H03M1/12 ,  H04N5/378 ,  H03M7/16 ,  H03M1/56 ,  H03K19/21 ,  H03K19/20

Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

公开(公告)号：US20220269482A1

公开(公告)日：2022-08-25

申请号：US17180520

申请日：2021-02-19

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Min Qu ,  Chao-Fang Tsai ,  Chun-Hsiang Chang

IPC: G06F7/507 ,  G06F7/575

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

公开(公告)号：US20210351768A1

公开(公告)日：2021-11-11

申请号：US16867399

申请日：2020-05-05

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Liang Zuo ,  Nijun Jiang ,  Min Qu ,  Xuelian Liu

IPC: H03K4/06 ,  H03M3/00 ,  H03M1/56 ,  H04N5/378

Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.