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    Implementation of reset functions in an SoC virtualized device
    11.
    发明授权
    Implementation of reset functions in an SoC virtualized device 有权

    公开(公告)号：US10296356B2

    公开(公告)日：2019-05-21

    申请号：US14944893

    申请日：2015-11-18

    Applicant: Oracle International Corporation

    Inventor： John R. Feehrer ,  Sriram Jayakumar ,  Rahoul Puri ,  Matthew Cohen ,  Julia Harper ,  Alan Adamson ,  John Johnson

    IPC: G06F11/00 ,  G06F9/4401 ,  G06F13/20

    Abstract: An apparatus and method for resetting a virtualized device are disclosed. The virtualized device may be coupled to a first port on a communication unit via a first link. The first port may send one or more instructions to the virtualized device via the first link using a first communication protocol. A processor may be configured to detect a reset condition for the virtualized device. In response to the detection of the reset condition for the virtualized device, the first port may disregard one or more transaction requests made by the virtualized device. The first port may further send an error message to the processor in response to receiving a Programmed Input/Output (PIO) request from the processor after the detection of the reset condition.

    Correctable Error Filtering for Input/Output Subsystem
    14.
    发明申请
    Correctable Error Filtering for Input/Output Subsystem 审中-公开

    公开(公告)号：US20170344419A1

    公开(公告)日：2017-11-30

    申请号：US15167601

    申请日：2016-05-27

    Applicant: Oracle International Corporation

    Inventor： John E. Watkins ,  Joseph R. Wright ,  John R. Feehrer

    IPC: G06F11/07

    CPC classification number: G06F11/0781 ,  G06F11/076

    Abstract: A switched fabric hierarchy (e.g., a PCIe hierarchy) may utilize hardware, firmware, and/or software for filtering duplicative or otherwise undesirable correctable error messages from reaching a root complex. An operating system of the root complex may detect a persistent stream or storm of correctable errors from a particular endpoint and activate filtering of correctable errors from that endpoint. A filtering device may receive filtering commands and parameters from the operating system, implement the filtering, and monitor further correctable errors from the offending device. While an offending device is being filtered, correctable error messages from the offending device may be masked from the operating system, while correctable error messages from other devices in the switched fabric hierarchy may be transmitted. At such time as the filtering device may detect that conditions for ending filtering of a device are met, the filtering device may cease filtering of the offending device and return monitoring responsibilities to the operating system.

    METHOD FOR STEERING DMA WRITE REQUESTS TO CACHE MEMORY
    16.
    发明申请
    METHOD FOR STEERING DMA WRITE REQUESTS TO CACHE MEMORY 有权
    用于将DMA写入请求转移到高速缓存存储器的方法

    公开(公告)号：US20150227312A1

    公开(公告)日：2015-08-13

    申请号：US14178626

    申请日：2014-02-12

    Applicant: Oracle International Corporation

    Inventor： John R. Feehrer ,  Hugh R. Kurth ,  Aron J. Silverton ,  Patrick Stabile

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F13/28 ,  G06F13/4027

    Abstract: A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.

    Abstract translation: 系统可以包括处理器，其可以包括高速缓冲存储器和直接存储器访问（DMA）控制器，I / O扩展总线上的外围设备以及耦合到I / O扩展总线和处理器的总线接口。 总线控制器可以确定从外围设备发送到处理器的数据分组是否包括具有可选期望高速缓存位置的高速缓存存储器的DMA写指令。 在确定对高速缓存存储器的DMA写指令被包括在数据分组中时，总线控制器可以格式化数据分组中的数据以存储在高速缓存中，并且接收所需的高速缓存位置或者确定缓存内的适当位置以存储 格式化数据。 如果高速缓存内的期望位置不能接收来自外围设备的更多数据，则总线控制器可以确定高速缓存内的替换位置。

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