公开(公告)号：US11709742B2

公开(公告)日：2023-07-25

申请号：US17648443

申请日：2022-02-02

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/00 ,  G06F11/20 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F11/2028 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0683 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/485 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2201/805 ,  G06F2212/452 ,  Y02D10/00

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US20200210185A1

公开(公告)日：2020-07-02

申请号：US16735564

申请日：2020-01-06

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06 ,  G06F11/20

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US20180246720A1

公开(公告)日：2018-08-30

申请号：US15441411

申请日：2017-02-24

Applicant: Oracle International Corporation

Inventor： Munsefar Khaleque ,  Nathan Sheeley ,  Mark Greenberg ,  Matthew Smittle ,  Paul Jordan

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.