摘要:
An original to be copied is electrooptically scanned point-by-point. The resulting imaging signals are stored in a first memory and then forwarded to a first image processing unit where the signals are electronically corrected to enhance the image of the original. The corrected signals are loaded into a second memory. A portion of the corrected signals is recalled from the second memory and sent to a third memory. This portion of the corrected signals is then transmitted to a second image processing unit and thereafter converted into a low-resolution video image which can be inspected to determine image quality. If image quality is satisfactory, the contents of the second memory are sent to an exposure unit which prints a high-resolution image of the original on copy material. Imaging signals for a second original are loaded into the first memory as the contents of the second memory are recalled for printing. The second processing unit functions to adjust the video image so that it closely corresponds to the printed image of the original.
摘要:
During the ongoing course of the exposure, the aperture area increases linearly to a maximum value and then stays at the maximum value, the instantaneous amount of exposure light therefore changing correspondingly, even if the ambient-light level remains constant during the exposure. A pulse generator includes a photodetector exposed to ambient light and generates a pulse train of light-dependent repetition frequency, the pulses of which are counted by a light-totalizing counter which eventually generates a terminate-exposure signal. Ideally, the repetition frequency should increase steplessly and linearly, for maximum accuracy, or second best increase stepwise in small steps to approximate to a stepless linear increase, but in order to use an extremely low number of stepwise frequency changes, without loss of system accuracy, no attempt is made to per se keep the light-indicating repetition frequency accurate. Instead, the number and amounts of the repetition-frequency changes are so established that, when the repetition frequency is plotted against elapsed exposure time, it is proportional to a piecewise linearization of the time integral curve of the exposure-aperture surface area, the constituent straight-line segments of the linearization being confined within a predetermined error-of-total-exposure tolerance range. In the case of a linear increase of aperture size concluding in maximum size, this corresponding to a quadratic followed by a straight-line rise of the time integral of the exposure-aperture surface area, the requisite time integral curve, despite its complexity, can, for example, be implemented using as few as only three or even as few as two stepwise changes of repetition frequency, without loss of system accuracy.
摘要:
An analog-to-digital converter is disclosed which utilizes a successive approximation register. The operation of the successive approximation register is so controlled that any analog signal within a dynamic range requiring more bits than the successive approximation register can hold can nonetheless be accurately converted within a predetermined tolerance.
摘要:
Headbox for a machine to produce a fiber web, in particular a paper, cardboard or tissue web from at least one fibrous suspension, having a headbox nozzle comprising an upper nozzle wall and a lower nozzle wall, as well as two side walls tapering to form an outlet, and having an inner chamber through which the fibrous suspension flows in flow direction during operation of headbox, whereby on upper nozzle wall of headbox nozzle a baffle is arranged on the outlet side which is movable by way of several elements and which extends across machine width, and which has a baffle protrusion and a baffle immersion depth and which has at least two surfaces—an upstream ramp surface and a subsequent main surface contacted by a fibrous suspension during operation of headbox. The inventive headbox is characterized in that between ramp surface of baffle and main surface of baffle at least one refraction surface which is in contact during operation of headbox with a fibrous suspension is provided on baffle.
摘要:
The invention relates to a headbox which comprises a feed device feeding the at least one fiber suspension, a perforated distribution pipe plate arranged immediately downstream thereof and having a plurality of channels arranged in lines and columns, an intermediate channel arranged downstream thereof, extending over the width of the headbox and having a plurality of means for dosing a fluid in partial fluid streams to the at least one fiber suspension in a preferably adjustable/controlled manner, the means being spaced apart from each other in the width direction of the headbox and the individual means comprising a plurality of dosing channels having respective dosing channel openings and an opening center line, arriving at different levels and being connected to a common supply channel. The headbox further comprises a downstream turbulence generator having a plurality of flow channels arranged in lines and columns and a headbox nozzle which is directly contiguous to the turbulence generator and which has a nozzle gap. The headbox according to the invention has a system pressure loss which is substantially composed of a first pressure loss between the feed device and the intermediate channel and a second pressure loss in the turbulence generator, the second pressure loss and the first pressure loss being in a ratio ranging from 8:1 to 1:1, preferably from 4:1 to 1:1, particularly from 2:1 to 1:1.
摘要:
A system for testing semiconductor devices is disclosed. In one embodiment, the test system being configured to be electrically connected via parallel wiring paths to a plurality of contact pins of a number of devices under test. The test system having at least one signal distribution matrix arranged in the wiring path to provide signals for testing and/or power supply to the devices.
摘要:
The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.
摘要:
A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal.
摘要:
A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.
摘要:
Memory module (1, 101, 201) having: at least one memory cell array (6, 106, 206), with the memory cells each being addressable by at least one address and being organized in organization units comprising a predetermined number of memory cells which can be driven jointly and at the same time; a clocked read/write control device (11, 111, 211), which is clocked with a first clock signal (CLK1) and which is coupled to the memory cell array (6, 106, 206), for writing data to and reading data from the memory cells as a function of address signals (ADR); a prefetch register unit (13, 113, 213), which is coupled to the read/write control device (11, 111, 211), for initial storage of data which is read from the memory cell array (6, 106, 206) and having two or more prefetch registers (14-17, 114-117, 214-217), whose respective register size corresponds to the predetermined number of memory cells in the organization units; a controlled switching device (23, 123, 223), which is coupled to the prefetch register unit (13, 113, 213), for outputting the data (DQs) which is initially stored in the prefetch registers (14-17, 114-117, 214-217) at data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201), with the switching device (23, 123, 223) successively coupling the prefetch registers (14-17, 114-117, 214-217) to the data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201) in a first operating mode of the memory module (1, 101, 201), controlled by a second clock signal (CLK2), with the number of data inputs/outputs (5, 105, 205) corresponding to the number of memory cells in the organization units, and coupling at least one of the prefetch registers (14-17, 114-117, 214-217) to the data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201) in a second operating mode controlled by at least one of the address signals (ADR).