公开(公告)号：US20060019455A1

公开(公告)日：2006-01-26

申请号：US10899359

申请日：2004-07-26

申请人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar

发明人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material (76) following the source/drain implant (74).

公开(公告)号：US20120180016A1

公开(公告)日：2012-07-12

申请号：US13004460

申请日：2011-01-11

申请人： PR Chidambaram ,  Prayag B. Patel ,  Foua Vang ,  Pratyush Kamal ,  Chock H Gan ,  Chethan Swamynathan

发明人： PR Chidambaram ,  Prayag B. Patel ,  Foua Vang ,  Pratyush Kamal ,  Chock H Gan ,  Chethan Swamynathan

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.

摘要翻译： 使用包括具有不同电压阈值的装置的标准单元架构制造的装置可以包括与第一通道长度相关联的第一组折线，其中第一组折线中的每个折线被基本恒定的间距分开。 该装置还可以包括与第二通道长度相关联并与第一组折线对准的第二组折线，其中第二组折线中的每条折线被基本恒定的间距横向隔开。 该装置还可以包括在第一组折线下方的第一有源区域和第二组折线下方的第二有源区域，其中第一有源区域和第二有源区域被分开小于170nm的距离。

公开(公告)号：US20050260858A1

公开(公告)日：2005-11-24

申请号：US11180149

申请日：2005-07-13

申请人： PR Chidambaram ,  Greg Baldwin

发明人： PR Chidambaram ,  Greg Baldwin

IPC分类号： H01L21/302 ,  H01L23/62 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

摘要翻译： 本发明提供了一种用于限制由在第二半导体结构（310）上由高电压从半导体衬底（302）内部产生的电场（314）引起的第一半导体结构（304）劣化的系统。 半导体器件（300）适于将场结构304的有效幅度减小到一些分数分量（320），或者使得该场接近第一结构的角度（322） 第一衬底区域（306） - 突出。 本发明的某些实施例提供：第一半导体结构的侧向凹陷以邻接设置在第二半导体结构和第一基底区域之间的隔离结构（312）; 所述第一半导体结构从所述隔离结构侧向退缩，以在其间形成护城河; 和在第一衬底区域内的反掺杂区域（316）。

公开(公告)号：US06818518B1

公开(公告)日：2004-11-16

申请号：US10602994

申请日：2003-06-24

申请人： PR Chidambaram

发明人： PR Chidambaram

IPC分类号： H01L21336

CPC分类号： H01L21/823418

摘要： The present invention provides a system and method for processing low voltage threshold transistors on a semiconductor wafer. The method may include: forming core transistors with drains on the semiconductor wafer; forming low voltage threshold transistors with drains on the semiconductor wafer; forming input output transistors with drains on the semiconductor wafer; forming a spacing layer over the core, low voltage and input output transistors; forming a first photoresist mask layer over the low voltage transistors; doping the drains of the core and the input output transistors, wherein the doping is a medium doping; forming a second photoresist mask layer over the input output transistors; and doping the drains of the core and the low voltage threshold transistors, wherein the doping is a medium doping.

摘要翻译： 本发明提供一种用于处理半导体晶片上的低电压阈值晶体管的系统和方法。 该方法可以包括：在半导体晶片上形成具有漏极的核心晶体管; 形成具有半导体晶片上的漏极的低电压阈值晶体管; 在半导体晶片上形成具有漏极的输入输出晶体管; 在芯上形成间隔层，低电压和输入输出晶体管; 在低压晶体管上形成第一光致抗蚀剂掩模层; 掺杂内核和输入输出晶体管的漏极，其中掺杂是中等掺杂; 在所述输入输出晶体管上形成第二光致抗蚀剂掩模层; 并且掺杂芯体的漏极和低电压阈值晶体管，其中掺杂是中掺杂。

公开(公告)号：US20070132027A1

公开(公告)日：2007-06-14

申请号：US11674545

申请日：2007-02-13

申请人： PR Chidambaram

发明人： PR Chidambaram

IPC分类号： H01L27/12

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长碳掺杂的硅，然后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的掺杂碳的硅靠近晶体管沟道并且用于向通道提供拉伸应力，从而有助于改善NMOS型晶体管器件中的载流子迁移率。

公开(公告)号：US07118977B2

公开(公告)日：2006-10-10

申请号：US10987674

申请日：2004-11-11

申请人： PR Chidambaram ,  Srinivasan Chakravarthi

发明人： PR Chidambaram ,  Srinivasan Chakravarthi

IPC分类号： H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/28044 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first recess is formed in an outer surface of the gate stack, and a first dopant is implanted into the gate stack after the first recess is formed. The first dopant diffuses inwardly from the outer surface of the gate stack that defines the first recess. The first dopant diffuses toward an interface between the gate stack and the semiconductor body. The first recess increases the concentration of the first dopant at the interface.

摘要翻译： 根据本发明的一个实施例，形成半导体器件的方法包括在半导体本体的外表面上形成栅叠层。 第一和第二侧壁体形成在栅极堆叠的相对侧上。 在栅堆叠的外表面上形成第一凹槽，并且在形成第一凹槽之后，将第一掺杂剂注入到栅叠层中。 第一掺杂剂从限定第一凹槽的栅叠层的外表面向内扩散。 第一掺杂剂朝向栅叠层和半导体本体之间的界面扩散。 第一凹槽增加界面处的第一掺杂剂的浓度。

公开(公告)号：US20050258494A1

公开(公告)日：2005-11-24

申请号：US10850751

申请日：2004-05-21

申请人： PR Chidambaram ,  Greg Baldwin

发明人： PR Chidambaram ,  Greg Baldwin

IPC分类号： H01L21/302 ,  H01L23/62 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

摘要翻译： 本发明提供了一种用于限制由在第二半导体结构（310）上由高电压从半导体衬底（302）内部产生的电场（314）引起的第一半导体结构（304）劣化的系统。 半导体器件（300）适于将如在结构304处实现的场的有效幅度减小到一些分数分量（320），或者使得该场接近第一结构的角度（322） 第一衬底区域（306） - 突出。 本发明的某些实施例提供：第一半导体结构的侧向凹陷以邻接设置在第二半导体结构和第一基底区域之间的隔离结构（312）; 所述第一半导体结构从所述隔离结构侧向退缩，以在其间形成护城河; 和在第一衬底区域内的反掺杂区域（316）。

公开(公告)号：US07208362B2

公开(公告)日：2007-04-24

申请号：US10877154

申请日：2004-06-25

申请人： PR Chidambaram

发明人： PR Chidambaram

IPC分类号： H01L21/336 ,  H01L21/8236

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

公开(公告)号：US20060099744A1

公开(公告)日：2006-05-11

申请号：US10987674

申请日：2004-11-11

申请人： PR Chidambaram ,  Srinivasan Chakravarthi

发明人： PR Chidambaram ,  Srinivasan Chakravarthi

IPC分类号： H01L21/8232 ,  H01L21/8234

CPC分类号： H01L21/28176 ,  H01L21/28044 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first recess is formed in an outer surface of the gate stack, and a first dopant is implanted into the gate stack after the first recess is formed. The first dopant diffuses inwardly from the outer surface of the gate stack that defines the first recess. The first dopant diffuses toward an interface between the gate stack and the semiconductor body. The first recess increases the concentration of the first dopant at the interface.

公开(公告)号：US07339215B2

公开(公告)日：2008-03-04

申请号：US11674545

申请日：2007-02-13

申请人： PR Chidambaram

发明人： PR Chidambaram

IPC分类号： H01L29/76

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长碳掺杂的硅，然后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的掺杂碳的硅靠近晶体管沟道并且用于向通道提供拉伸应力，从而有助于改善NMOS型晶体管器件中的载流子迁移率。