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公开(公告)号：US09813651B2
公开(公告)日：2017-11-07
申请号：US14579592
申请日：2014-12-22
Inventor： Mitsuyoshi Mori , Hirohisa Ohtsuki , Yoshiyuki Ohmori , Yoshihiro Sato , Ryohei Miyagawa
IPC: H04N5/335 , H04N3/14 , H04N5/378 , H01L27/146 , H04N5/3745
CPC classification number: H04N5/378 , H01L27/14603 , H01L27/1461 , H01L27/1464 , H01L27/14645 , H04N5/3745
Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.
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公开(公告)号：US12266666B2
公开(公告)日：2025-04-01
申请号：US18107834
申请日：2023-02-09
Inventor： Tokuhiko Tamaki , Hirohisa Ohtsuki , Ryohei Miyagawa , Motonori Ishii
IPC: H01L27/146 , H04N25/77 , H04N25/709
Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
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公开(公告)号：US10818707B2
公开(公告)日：2020-10-27
申请号：US16130664
申请日：2018-09-13
Inventor： Tokuhiko Tamaki , Hirohisa Ohtsuki , Ryohei Miyagawa , Motonori Ishii
IPC: H01L27/146 , H04N5/3745 , H04N5/369
Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
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公开(公告)号：US10021330B2
公开(公告)日：2018-07-10
申请号：US15204006
申请日：2016-07-07
Inventor： Hiroshi Kubo , Hirohisa Ohtsuki , Kunihiko Hara
CPC classification number: H04N5/3742 , H04N5/347 , H04N5/357 , H04N5/374 , H04N5/3745 , H04N5/37455 , H04N5/37457 , H04N5/378 , H04N9/045 , H04N2209/042 , H04N2209/045
Abstract: In a solid-state image capturing device, one or more vertical signal lines are disposed along one of columns of a pixel portion, and each of the vertical signal lines is divided into two parts between an upper region and a lower region of the pixel portion. Pixel signals output from a plurality of pixels of the one of the columns are read out to a plurality of column readout circuits through two or more parts of the vertical signal lines including the two parts of the one or more vertical signal lines disposed along the one of the columns. A division position of one vertical signal line among the vertical signal lines disposed in the pixel portion is different from a division position of another vertical signal line among the vertical signal lines in a row direction.
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