公开(公告)号：US20120176173A1

公开(公告)日：2012-07-12

申请号：US13174078

申请日：2011-06-30

Applicant: Chittoor PARTHASARATHY ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

Inventor： Chittoor PARTHASARATHY ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: H03K3/02 ,  H03K3/00

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 我们提出一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US20120032291A1

公开(公告)日：2012-02-09

申请号：US13198458

申请日：2011-08-04

Applicant: Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

Inventor： Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

IPC: H01L25/16

CPC classification number: H01L25/16 ,  H01L21/76838 ,  H01L23/481 ,  H01L25/0652 ,  H01L31/02245 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15192 ,  Y02E10/50 ,  H01L2224/81

Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.

Abstract translation: 一种独立装置，包括具有其前表面的硅晶片，该硅晶片包括形成光伏电池的第一导电类型的第一层和第二导电类型的第二层; 从第一层的后表面穿过晶片的第一通孔和从第二层的后表面穿过晶片的第二过孔; 在晶片的后表面上的金属化水平，这些金属化水平的外部水平限定接触垫; 形成在金属化层之一中的天线; 以及组装在所述垫上的一个或多个芯片; 金属化水平被成形为在装置的不同元件之间提供选定的互连。

公开(公告)号：US07853854B2

公开(公告)日：2010-12-14

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US20080052596A1

公开(公告)日：2008-02-28

申请号：US11834198

申请日：2007-08-06

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: G06F11/10

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6566

Abstract: The blocks may be stored temporarily and successively in an input memory before decoding them successively in an iterative manner. The input memory has a memory size allowing the storage of more than two blocks. A current indication representative of a permitted maximum number of iterations for decoding a current block may be defined. The current indication may be initialized to a reference number of iterations increased by an additional number of iterations dependent on the additional memory size of the input memory allowing supplementary storage beyond two blocks. The current block may be decoded until a decoding criterion is satisfied or so long as the number of iterations has not reached the current indication while a first subsequent block and possibly a part of a second subsequent block are stored in the input memory. The current indication may be updated for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract translation: 这些块可以以迭代的方式连续解码之前临时且相继地存储在输入存储器中。 输入存储器具有允许存储多于两个块的存储器大小。 可以定义表示用于解码当前块的允许的最大迭代次数的当前指示。 当前指示可以被初始化为依赖于输入存储器的附加存储器大小的附加数量的迭代增加的参考迭代次数，允许超过两个块的补充存储。 可以解码当前块，直到满足解码标准，或者只要迭代次数尚未达到当前指示，而第一后续块和可能的第二后续块的一部分存储在输入存储器中。 作为对当前块进行解码执行的迭代次数的函数的函数，可以更新当前指示以便解码第一后续块。

公开(公告)号：US20070198896A1

公开(公告)日：2007-08-23

申请号：US11563595

申请日：2006-11-27

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1105 ,  H03M13/152 ,  H03M13/1555 ,  H03M13/1595 ,  H03M13/2906

Abstract: A concatenated channel decoding method wherein the bits of a set of N1 bits decoded using a first iterative block decoding algorithm and intended to be decoded using a second block decoding algorithm, are sent in parallel in at least one subset of P bits to a buffer for temporary storage. The decoding method comprises receiving in parallel at least one subset of Q bits belonging to the set of N1 bits sent to the buffer, detecting errors with the help of the second decoding algorithm, based on the bits decoded using the first decoding algorithm, and correcting the bits stored in the buffer as a function of possible errors detected. Detecting errors and/or the correcting the stored bits comprise a parallel processing of the bits of each subset of Q bits received.

Abstract translation: 一种级联信道解码方法，其中使用第一迭代块解码算法解码并且想要使用第二块解码算法进行解码的一组N1比特的比特在P比特的至少一个子集中并行发送到缓冲器， 临时存储。 解码方法包括：并行地接收属于发送到缓冲器的N1比特组的Q比特的至少一个子集，借助于第二解码算法检测错误，基于使用第一解码算法解码的比特，以及校正 存储在缓冲器中的位可以作为检测到的可能错误的函数。 检测错误和/或校正所存储的比特包括接收的Q位的每个子集的比特的并行处理。

公开(公告)号：US20070198895A1

公开(公告)日：2007-08-23

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US07127651B2

公开(公告)日：2006-10-24

申请号：US10914306

申请日：2004-08-09

Applicant: Pascal Urard

Inventor： Pascal Urard

IPC: G01R31/28

CPC classification number: H03H17/0294 ,  H03H17/0621

Abstract: A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The input and output digital sampling values correspond to identical respective reconstruction curves, and the output frequency may be greater than or less than the input frequency. Each cell includes a storage element, two multipliers and two adders.

Abstract translation: 采样率转换器包括串联连接的相同单元的链。 链的第一单元的输入根据输入频率接收输入数字采样值。 然后，第一单元的输出根据输出频率输出输出数字采样值。 输入和输出数字采样值对应于相同的相应重建曲线，并且输出频率可以大于或小于输入频率。 每个单元包括存储元件，两个乘法器和两个加法器。

公开(公告)号：US20050210350A1

公开(公告)日：2005-09-22

申请号：US10914306

申请日：2004-08-09

Applicant: Pascal Urard

Inventor： Pascal Urard

IPC: H03H17/02 ,  H03H17/06 ,  G01R31/28 ,  G06F11/00

CPC classification number: H03H17/0294 ,  H03H17/0621

Abstract: A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The input and output digital sampling values correspond to identical respective reconstruction curves, and the output frequency may be greater than or less than the input frequency. Each cell includes a storage element, two multipliers and two adders.

Abstract translation: 采样率转换器包括串联连接的相同单元的链。 链的第一单元的输入根据输入频率接收输入数字采样值。 然后，第一单元的输出根据输出频率输出输出数字采样值。 输入和输出数字采样值对应于相同的相应重建曲线，并且输出频率可以大于或小于输入频率。 每个单元包括存储元件，两个乘法器和两个加法器。

公开(公告)号：US08327033B2

公开(公告)日：2012-12-04

申请号：US12150599

申请日：2008-04-29

Applicant: Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

Inventor： Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

IPC: G06F3/00 ,  G06F13/00

CPC classification number: H03M13/2775 ,  H03M13/2957 ,  H04L1/0071

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract translation: 提供了一种包括耦合到输入和输出的输入，输出和数据交织器的数据交织设备。 输入接收来自多个处理块的数据。 输出将交错数据传送到多个处理块。 数据交织器包括控制器，至少一个互连模块和多个存储器。 控制器准备数据到内存分配数据结构。 至少一个互连模块根据数据到存储器分配数据结构并行地切换数据，并且对并行地同时切换的所有数据执行相同的操作。 多个存储器存储切换的数据。 数据交织器交织从输入接收的数据，并在输出端提供交错数据。

公开(公告)号：US08046658B2

公开(公告)日：2011-10-25

申请号：US11834198

申请日：2007-08-06

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6566

Abstract: A method is for decoding a succession of blocks of data encoded with an LDPC code. The method includes storing the blocks temporarily and successively in an input memory before decoding the blocks successively in an iterative manner, the input memory having a memory size for storage of at least two blocks, and defining a current indication representative of a threshold number of iterations for decoding a current block. The method includes decoding the current block until a decoding criterion is satisfied or so long as a number of iterations performed for decoding the current block has not reached the current indication while at least one of a first subsequent block and a part of a second subsequent block are stored in the input memory, and updating the current indication for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract translation: 一种用于解码用LDPC码编码的数据块序列的方法。 该方法包括：以迭代方式连续解码块之前临时并连续地存储块，输入存储器具有用于存储至少两个块的存储器大小，并且定义表示阈值迭代次数的当前指示 用于解码当前块。 该方法包括解码当前块直到满足解码标准，或者只要对当前块解码执行的迭代次数尚未达到当前指示，而第一后续块和第二后续块的一部分中的至少一个 被存储在输入存储器中，并且根据为解码当前块执行的迭代次数来更新当前用于解码第一后续块的指示。