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11.发明授权Mechanism for processor power state aware distribution of lowest priority interrupts 失效处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07761720B2
公开(公告)日：2010-07-20
申请号：US11704760
申请日：2007-02-09
IPC分类号： G06F1/26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
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12.发明申请公开(公告)号：US20090070510A1
公开(公告)日：2009-03-12
申请号：US11966356
申请日：2007-12-28
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
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13.发明授权Apparatus and method for enumeration of processors during hot-plug of a compute node 失效在计算节点的热插拔期间枚举处理器的装置和方法公开(公告)号：US07493438B2
公开(公告)日：2009-02-17
申请号：US09971211
申请日：2001-10-03
申请人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
发明人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.
摘要翻译： 描述了在计算节点的热插拔期间枚举处理器的装置和方法。 该方法包括响应于热插拔复位的一个或多个处理器的枚举。 枚举被提供给其中计算节点被热插拔的系统架构操作系统。 枚举完成后，响应于操作系统激活请求启动计算节点。 因此，一旦设备枚举以及资源枚举完成，处理器存储器节点的一个或多个处理器被激活，使得操作系统可以开始利用热插拔的计算节点的处理器。
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公开(公告)号：US07117311B1
公开(公告)日：2006-10-03
申请号：US10027397
申请日：2001-12-19
申请人： Linda J. Rankin , Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , David J. O'Shea
发明人： Linda J. Rankin , Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , David J. O'Shea
IPC分类号： G06F13/00
CPC分类号： G06F12/0822 , G06F12/0808 , G06F12/0813 , G06F12/0831
摘要： A computing device maintains coherency while supporting addition and removal of memory caching agents without rebooting the computing device.
摘要翻译： 计算设备维护一致性，同时支持添加和删除内存高速缓存代理，而无需重新启动计算设备。
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15.发明授权Processor selection for an interrupt based on willingness to accept the interrupt and on priority 有权处理器根据意愿接受中断和优先级中断进行选择公开(公告)号：US08032681B2
公开(公告)日：2011-10-04
申请号：US11966356
申请日：2007-12-28
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
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16.发明授权Apparatus and method for enumeration of processors during hot-plug of a compute node 有权在计算节点的热插拔期间枚举处理器的装置和方法公开(公告)号：US07822900B2
公开(公告)日：2010-10-26
申请号：US12271725
申请日：2008-11-14
申请人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
发明人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.
摘要翻译： 描述了在计算节点的热插拔期间枚举处理器的装置和方法。 该方法包括响应于热插拔复位的一个或多个处理器的枚举。 枚举被提供给其中计算节点被热插拔的系统架构操作系统。 枚举完成后，响应于操作系统激活请求启动计算节点。 因此，一旦设备枚举以及资源枚举完成，处理器存储器节点的一个或多个处理器被激活，使得操作系统可以开始利用热插拔的计算节点的处理器。
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17.发明申请APPARATUS AND METHOD FOR ENUMERATION OF PROCESSORS DURING HOT-PLUG OF A COMPUTE NODE 有权在计算机节点热插拔过程中进行处理器的设计和方法公开(公告)号：US20090106471A1
公开(公告)日：2009-04-23
申请号：US12271725
申请日：2008-11-14
申请人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
发明人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.
摘要翻译： 描述了在计算节点的热插拔期间枚举处理器的装置和方法。 该方法包括响应于热插拔复位的一个或多个处理器的枚举。 枚举被提供给其中计算节点被热插拔的系统架构操作系统。 枚举完成后，响应于操作系统激活请求启动计算节点。 因此，一旦设备枚举以及资源枚举完成，处理器存储器节点的一个或多个处理器被激活，使得操作系统可以开始利用热插拔的计算节点的处理器。
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公开(公告)号：US07000102B2
公开(公告)日：2006-02-14
申请号：US09895580
申请日：2001-06-29
申请人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
发明人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
CPC分类号： G06F1/30 , G06F1/3203 , G06F9/4418
摘要： One aspect of the invention relates to a method for supporting hibernation despite the presence of hot-plugged nodes and non-deterministic boot operations. The method comprises invoking a management interrupt in response to a Hibernate request. The management interrupt is used to obtain and store platform configuration information into a non-volatile storage location. The platform configuration information includes data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence as well as a boot node identifier and a listing of an order in which processors of the platform are initialized.
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19.发明授权公开(公告)号：US06917999B2
公开(公告)日：2005-07-12
申请号：US09895692
申请日：2001-06-29
申请人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
发明人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
CPC分类号： G06F9/5077 , G06F9/4411
摘要： One aspect of the invention relates to creation of a container object being part of software that is stored in platform readable medium and executed by a processor within a platform. The container comprises (i) a hardware identification object to identify to an operating system of the platform that a type of device represented by the container object is a node and (ii) a plurality of component objects to identify constituent components of the node. Another aspect of the invention is the distribution of BIOS to handle initiation of components of a substrate in response to hot-plug addition of that substrate.
摘要翻译： 本发明的一个方面涉及作为存储在平台可读介质中并由平台内的处理器执行的软件的一部分的容器对象的创建。 容器包括（i）用于向平台的操作系统识别由容器对象表示的设备的类型是节点的硬件标识对象，以及用于识别节点的组成部件的多个组件对象。 本发明的另一方面是响应于该基板的热插入添加而分配BIOS以处理基板的部件的启动。
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20.发明授权Mechanism for processor power state aware distribution of lowest priority interrupt 有权处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07191349B2
公开(公告)日：2007-03-13
申请号：US10330622
申请日：2002-12-26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
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