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1.发明授权公开(公告)号：US07627706B2
公开(公告)日：2009-12-01
申请号：US11850782
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括用于接收物理处理器标识号的逻辑中断识别号码创建逻辑，并通过使用物理处理器标识号创建逻辑处理器标识号。 每个逻辑处理器识别号对应于物理处理器识别号之一，并且逻辑处理器标识号各自包括处理器群标识号和群内标识号。 每个处理器集群标识号被形成为包括从相应的物理处理器标识号码位置移位的一组位，并且群内标识号分别响应于对应的物理处理器标识的其他位的值而形成 数。 描述其他实施例。
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公开(公告)号：US20090070511A1
公开(公告)日：2009-03-12
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
IPC分类号： G06F13/24
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
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3.发明申请公开(公告)号：US20090070510A1
公开(公告)日：2009-03-12
申请号：US11966356
申请日：2007-12-28
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
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公开(公告)号：US07769938B2
公开(公告)日：2010-08-03
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
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5.发明授权Processor selection for an interrupt based on willingness to accept the interrupt and on priority 有权处理器根据意愿接受中断和优先级中断进行选择公开(公告)号：US08032681B2
公开(公告)日：2011-10-04
申请号：US11966356
申请日：2007-12-28
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
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公开(公告)号：US20090070551A1
公开(公告)日：2009-03-12
申请号：US11850782
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Grossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Grossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
IPC分类号： G06F15/82
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括用于接收物理处理器标识号的逻辑中断识别号码创建逻辑，并通过使用物理处理器标识号创建逻辑处理器标识号。 每个逻辑处理器识别号对应于物理处理器识别号之一，并且逻辑处理器标识号各自包括处理器群标识号和群内标识号。 每个处理器集群标识号被形成为包括从相应的物理处理器标识号码位置移位的一组位，并且群内标识号分别响应于对应的物理处理器标识的其他位的值而形成 数。 描述其他实施例。
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公开(公告)号：US07640384B2
公开(公告)日：2009-12-29
申请号：US11903249
申请日：2007-09-20
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.
摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 在一个实施例中，提供了存储用于执行监视机制的功能的指令的存储器。 监视机制具有使处理器响应于事件退出休眠状态的第一逻辑，其中退出休眠状态包括恢复处理在休眠状态期间被处理器放弃的处理资源的控制。 所述监视机制具有第二逻辑，以在所述处理器退出所述睡眠状态之后禁用与竞争锁相关联的节点的监视。
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8.发明授权Mechanism for processor power state aware distribution of lowest priority interrupt 有权处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07191349B2
公开(公告)日：2007-03-13
申请号：US10330622
申请日：2002-12-26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
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9.发明授权Mechanism for processor power state aware distribution of lowest priority interrupts 失效处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07761720B2
公开(公告)日：2010-07-20
申请号：US11704760
申请日：2007-02-09
IPC分类号： G06F1/26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
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10.发明授权Apparatus and method for enumeration of processors during hot-plug of a compute node 失效在计算节点的热插拔期间枚举处理器的装置和方法公开(公告)号：US07493438B2
公开(公告)日：2009-02-17
申请号：US09971211
申请日：2001-10-03
申请人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
发明人： Shivnandan D. Kaushik , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.
摘要翻译： 描述了在计算节点的热插拔期间枚举处理器的装置和方法。 该方法包括响应于热插拔复位的一个或多个处理器的枚举。 枚举被提供给其中计算节点被热插拔的系统架构操作系统。 枚举完成后，响应于操作系统激活请求启动计算节点。 因此，一旦设备枚举以及资源枚举完成，处理器存储器节点的一个或多个处理器被激活，使得操作系统可以开始利用热插拔的计算节点的处理器。
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