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公开(公告)号：US08040265B2
公开(公告)日：2011-10-18
申请号：US11946850
申请日：2007-11-29
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
IPC分类号： H03M3/00
CPC分类号： H04L25/03834 , H04L25/38 , H04L27/0014 , H04L2027/0024
摘要： The disclosed invention provides apparatus and methods that can convert frequencies of time-encoded signals. In one aspect, a down-converter circuit includes low-pass filters, a switch, a time encoder, and an output low-pass filter. In another aspect, an up-converter circuit includes an analog or digital input time encoder, low-pass filters, a switch, an output time encoder, and a time-encoded band-pass filter. In yet another aspect, a complete receiver system is provided. The receiver system can operate effectively with signals in the radio frequency range.
摘要翻译： 所公开的发明提供了可以转换时间编码信号的频率的装置和方法。 一方面，下变频电路包括低通滤波器，开关，时间编码器和输出低通滤波器。 在另一方面，上变换器电路包括模拟或数字输入时间编码器，低通滤波器，开关，输出时间编码器和时间编码带通滤波器。 在另一方面，提供了完整的接收机系统。 接收机系统可以在射频范围内的信号中有效地进行操作。
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公开(公告)号：US07822698B1
公开(公告)日：2010-10-26
申请号：US11726860
申请日：2007-03-23
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
IPC分类号： G06J1/00
摘要： A neural network has an array of interconnected processors, each processor operating either the pulse domain or spike domain. Each processor has (i) first inputs selectively coupled to other processors in the array of processors, each first input having an associated 1 bit DAC coupled to a summing node, (ii) second inputs selectively coupled to inputs of the neural network, the second inputs having current generators associated therewith coupled to said summing node, (iii) a filter/integrator for generating an analog signal corresponding to current arriving at the summing node, (iv) an optional nonlinear element coupled to the filter/integrator, and (v) an analog-to-pulse converter, if the processors operate in the pulse domain, or an analog-to-spike convertor, if the processors operate in the spike domain, for converting an analog signal output by the optional nonlinear element or by the filter/integrator to either the pulse domain or spike domain, and providing the converted analog signal as an unquantized pulse or spike domain signal at an output of the processor. The array of processors are selectively interconnected with either unquantized pulse domain or spike domain signals.
摘要翻译： 神经网络具有互连的处理器阵列，每个处理器操作脉冲域或尖峰域。 每个处理器具有（i）选择性地耦合到处理器阵列中的其他处理器的第一输入，每个第一输入具有耦合到求和节点的相关联的1比特DAC，（ii）选择性地耦合到所述神经网络的输入的第二输入， 输入，其具有与其相关联的电流发生器耦合到所述求和节点，（iii）滤波器/积分器，用于产生对应于到达求和节点的电流的模拟信号，（iv）耦合到滤波器/积分器的可选非线性元件，（v ）模拟脉冲转换器，如果处理器在脉冲域中操作，或者模拟到尖峰转换器，如果处理器在尖峰域中操作，则用于转换由可选非线性元件输出的模拟信号或由 滤波器/积分器到脉冲域或尖峰域，并且在处理器的输出处将经转换的模拟信号提供为非量化脉冲或尖峰域信号。 处理器阵列与非量化脉冲域或尖峰域信号选择性互连。
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公开(公告)号：US08959040B1
公开(公告)日：2015-02-17
申请号：US13415812
申请日：2012-03-08
CPC分类号： G06N3/0635 , G06N3/049 , G06N3/06
摘要： A spike timing dependent plasticity (STDP) apparatus, neuromorphic synapse system and a method provide STDP processing of spike signals. The STDP apparatus includes a first leaky integrator to receive a first spike signal and a second leaky integrator to receive a second spike signal. An output of the first leaky integrator is gated according to the second spike signal to produce a first gated integrated signal and an output of the second leaky integrator is gated according to the first spike signal to produce a second gated integrated signal. The STDP apparatus further includes an output integrator to integrate a difference of the first and second gated integrated signals to produce a weighted signal. The system includes a synapse core and the STDP apparatus. The method includes integrating the spike signals, gating the integrated signals and integrating a difference of the gated integrated signals.
摘要翻译： 尖峰定时依赖可塑性（STDP）装置，神经突触突触系统和一种方法提供尖峰信号的STDP处理。 STDP装置包括用于接收第一尖峰信号的第一泄漏积分器和用于接收第二尖峰信号的第二泄漏积分器。 第一泄漏积分器的输出根据第二尖峰信号选通，以产生第一门控积分信号，并且第二泄漏积分器的输出根据第一尖峰信号选通，以产生第二门控积分信号。 STDP装置还包括输出积分器，用于积分第一和第二门控积分信号的差以产生加权信号。 该系统包括突触核心和STDP设备。 该方法包括对尖峰信号进行积分，门控积分信号并积分门控积分信号的差值。
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14.发明授权High-order time encoder based neuron circuit using a hysteresis quantizer, a one bit DAC, and a second order filter 有权使用滞后量化器的高阶时间编码器神经元电路，一位DAC和二阶滤波器公开(公告)号：US08595157B2
公开(公告)日：2013-11-26
申请号：US13151763
申请日：2011-06-02
IPC分类号： G06F15/00
摘要： A spike domain circuit responsive to analog and/or spike domain input signals. The spike domain circuit has a hysteresis quantizer for generating a spike domain output signal z(t); a one bit DAC having an input which is coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and having an output which is coupled to a current summing node; and a second order filter stage having two inputs, one of said two inputs being coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and the other of the two inputs being coupled to receive current summed at said current summing node. The second order filter stage has an output coupled to an input of the hysteresis quantizer. The current summing node also receives signals related to the analog and/or spike domain input signals to which the circuit is responsive. The circuit may serve as a neural node and many such circuits may be utilized together to model neurons with complex biological dynamics.
摘要翻译： 响应于模拟和/或尖峰域输入信号的尖峰域电路。 尖峰域电路具有用于产生尖峰域输出信号z（t）的滞后量化器; 一个一比特DAC，其具有被耦合以接收由滞后量化器输出的尖峰域输出信号z（t）并具有耦合到当前求和节点的输出的输入; 和具有两个输入的二阶滤波器级，所述两个输入中的一个被耦合以接收由滞后量化器输出的尖峰域输出信号z（t），并且两个输入中的另一个被耦合以接收在所述当前求和 节点。 二阶滤波器级具有耦合到迟滞量化器的输入的输出。 当前求和节点还接收与电路响应的模拟和/或尖峰域输入信号有关的信号。 该电路可以用作神经节点，并且许多这样的电路可以一起使用以用复杂的生物动力学来建模神经元。
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15.发明授权Asynchronous pulse processing apparatus and method providing signal reverberation 有权异步脉冲处理装置和方法提供信号混响公开(公告)号：US08390500B1
公开(公告)日：2013-03-05
申请号：US12815366
申请日：2010-06-14
IPC分类号： H03M1/38
CPC分类号： G06N3/049
摘要： An asynchronous pulse processing (APP) apparatus, APP system and a method of signal reverberation employ asynchronous pulse processing to provide signal reverberation. The APP apparatus includes a gain block configured to scale an input signal by a first scale value and a summation block configured to produce a composite signal. The composite signal represents the scaled input signal minus an input summation signal multiplied by a reverberation signal, minus the reverberation signal scaled by a second scale value, and plus a function-modified feedback signal. The APP apparatus further includes an integrator and a time encoder configured to produce the reverberation signal from the composite signal. The APP system includes a plurality of APP apparatuses as APP channels. The method of signal reverberation includes generating a composite signal from a scaled input signal, and integrating and time encoding the composite signal to produce a reverberation signal.
摘要翻译： 异步脉冲处理（APP）装置，APP系统和信号混响方法采用异步脉冲处理来提供信号混响。 APP装置包括增益块，其被配置为按照第一刻度值缩放输入信号，以及被配置为产生复合信号的求和块。 复合信号表示经缩放的输入信号减去乘以混响信号的输入求和信号，减去由第二比例值缩放的混响信号，并加上函数修正的反馈信号。 APP装置还包括积分器和配置成从复合信号产生混响信号的时间编码器。 APP系统包括作为APP通道的多个APP装置。 信号混响的方法包括从缩放的输入信号生成复合信号，并对复合信号进行积分和时间编码以产生混响信号。
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公开(公告)号：US20120310871A1
公开(公告)日：2012-12-06
申请号：US13151763
申请日：2011-06-02
IPC分类号： G06N3/06
摘要： A spike domain circuit responsive to analog and/or spike domain input signals. The spike domain circuit has a hysteresis quantizer for generating a spike domain output signal z(t); a one bit DAC having an input which is coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and having an output which is coupled to a current summing node; and a second order filter stage having two inputs, one of said two inputs being coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and the other of the two inputs being coupled to receive current summed at said current summing node. The second order filter stage has an output coupled to an input of the hysteresis quantizer. The current summing node also receives signals related to the analog and/or spike domain input signals to which the circuit is responsive. The circuit may serve as a neural node and many such circuits may be utilized together to model neurons with complex biological dynamics.
摘要翻译： 响应于模拟和/或尖峰域输入信号的尖峰域电路。 尖峰域电路具有用于产生尖峰域输出信号z（t）的滞后量化器; 一个一比特DAC，其具有被耦合以接收由滞后量化器输出的尖峰域输出信号z（t）并具有耦合到当前求和节点的输出的输入; 和具有两个输入的二阶滤波器级，所述两个输入中的一个被耦合以接收由滞后量化器输出的尖峰域输出信号z（t），并且两个输入中的另一个被耦合以接收在所述当前求和 节点。 二阶滤波器级具有耦合到迟滞量化器的输入的输出。 当前求和节点还接收与电路响应的模拟和/或尖峰域输入信号有关的信号。 该电路可以用作神经节点，并且许多这样的电路可以一起使用以用复杂的生物动力学来建模神经元。
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公开(公告)号：US07965216B1
公开(公告)日：2011-06-21
申请号：US12262691
申请日：2008-10-31
申请人： Peter Petre , Jose Cruz-Albrecht
发明人： Peter Petre , Jose Cruz-Albrecht
IPC分类号： H03M1/12
摘要： A system for analog-to-digital signal conversion featuring compressed sensing analog-to-digital converter systems. An analog signal is connected to a time encoder having a pulse frequency. The analog signal frequency is higher than the pulse frequency. The time encoder is configured to generate an excitation vector including a plurality of projection values of the analog signal into a plurality of testing basis functions, and a plurality of known basis functions. The output of the time encoder is connected to an input of a pulse domain demultiplexer, and the pulse domain demultiplexer is connected to the pulse-to-asynchronous digital converter in a predetermined sequence. The pulse-to-asynchronous digital converter is connected to the asynchronous-digital-to-synchronous digital converter in a predetermined sequence. The asynchronous-digital-to-synchronous digital converter is connected a digital signal processor configured to output an estimate of the analog signal. Methods to make the foregoing structure are also described.
摘要翻译： 一种具有压缩感测模数转换器系统的模数转换信号转换系统。 模拟信号连接到具有脉冲频率的时间编码器。 模拟信号频率高于脉冲频率。 时间编码器被配置为将包括模拟信号的多个投影值的激励矢量生成到多个测试基函数中，以及多个已知的基函数。 时间编码器的输出连接到脉冲域解复用器的输入，脉冲域解复用器以预定顺序连接到脉冲到异步数字转换器。 脉冲到异步数字转换器以预定的顺序连接到异步数字到同步数字转换器。 异步数字到同步数字转换器连接有配置为输出模拟信号的估计的数字信号处理器。 还描述了制造上述结构的方法。
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公开(公告)号：US07592939B1
公开(公告)日：2009-09-22
申请号：US12118475
申请日：2008-05-09
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
IPC分类号： H03M1/66
CPC分类号： H03M3/02
摘要： A system and method for making a digital encoder. The digital encoder has a digital-to-analog converter having multiple inputs and an output. The encoder also has an integrator having an input and an output, wherein the output of the digital-to-analog converter is connected to the input of the integrator. A quantizer has an input and an output, wherein the output of the integrator is connected to the input of the quantizer, and the output of the quantizer is connected to one of the plurality of inputs of the digital-to-analog converter. Methods to make the foregoing structure are also described.
摘要翻译： 一种用于制作数字编码器的系统和方法。 数字编码器具有具有多个输入和输出的数模转换器。 编码器还具有具有输入和输出的积分器，其中数模转换器的输出连接到积分器的输入端。 量化器具有输入和输出，其中积分器的输出连接到量化器的输入，并且量化器的输出连接到数模转换器的多个输入之一。 还描述了制作上述结构的方法。
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公开(公告)号：US11150327B1
公开(公告)日：2021-10-19
申请号：US16044179
申请日：2018-07-24
申请人： Qin Jiang , Youngkwan Cho , Nigel D. Stepp , Steven W. Skorheim , Vincent De Sapio , Jose Cruz-Albrecht , Praveen K. Pilly
发明人： Qin Jiang , Youngkwan Cho , Nigel D. Stepp , Steven W. Skorheim , Vincent De Sapio , Jose Cruz-Albrecht , Praveen K. Pilly
摘要： A system configured to identify a target in a synthetic aperture radar signal includes: a feature extractor configured to extract a plurality of features from the synthetic aperture radar signal; an input spiking neural network configured to encode the features as a first plurality of spiking signals; a multi-layer recurrent neural network configured to compute a second plurality of spiking signals based on the first plurality of spiking signals; a readout neural layer configured to compute a signal identifier based on the second plurality of spiking signals; and an output configured to output the signal identifier, the signal identifier identifying the target.
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