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公开(公告)号：US12113552B2
公开(公告)日：2024-10-08
申请号：US18066276
申请日：2022-12-14
Applicant: Asahi Kasei Microdevices Corporation
Inventor： Kazuma Ohara
Abstract: Provided is a delta-sigma modulator including a first integral unit configured to integrate an input analog signal, a second integral unit configured to integrate a signal output by the first integral unit, a quantizer configured to quantize a signal output by the second integral unit, a DA converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit, and a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, in which the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period.
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公开(公告)号：US20190173513A1
公开(公告)日：2019-06-06
申请号：US16095722
申请日：2017-04-05
Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Inventor： Takashi MAEHATA
CPC classification number: H03M3/30 , H03M3/02 , H03M3/32 , H03M3/402 , H03M3/422 , H04B1/04 , H04B1/0475 , H04B1/44 , H04B1/52 , H04W88/085
Abstract: Provided is a transmission system including: a signal processing apparatus 2 configured to transmit, via a signal cable 4, a delta-sigma modulated signal obtained by performing delta-sigma modulation on a transmission signal that is an RF signal; and a wireless apparatus 3 configured to transmit, via the signal cable 4, a reception signal that is an RF signal. The signal processing apparatus 2 transmits the delta-sigma modulated signal to the wireless apparatus 3, and the wireless apparatus 3 transmits the reception signal to the signal processing apparatus 2. In the delta-sigma modulated signal, quantization noise is suppressed at the frequency of the reception signal. The reception signal is transmitted to the signal processing apparatus 2 while the delta-sigma modulated signal is being transmitted to the wireless apparatus 3.
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公开(公告)号：US20180139802A1
公开(公告)日：2018-05-17
申请号：US15569802
申请日：2016-03-07
Applicant: NEC Corporation
Inventor： Shinichi HORI , Tomoyuki YAMASE
CPC classification number: H04W88/085 , H03L7/08 , H03L7/0807 , H03M3/02 , H03M3/30 , H03M3/40 , H03M3/458 , H03M3/50 , H04B1/40 , H04B10/25752 , H04B10/40 , H04B2210/006 , H04L27/36 , H04Q11/0067 , H04Q11/0071
Abstract: Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (1); and a remote unit (3) that converts a baseband signal generated by the center unit (1) into a high-frequency signal and emits the high-frequency signal from an antenna (12). The center unit (1) includes a 1-bit modulator (5) that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal. The remote unit (3) includes: a local generation unit (10) that extracts the clock signal from the 1-bit signal output from the center unit (1), and generates a local signal using the extracted clock signal as a reference signal; a filter (13) that extracts a desired band component from the 1-bit signal; and an up-converter (14) that converts, using the local signal, an output signal of the filter into a high-frequency signal.
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4.发明授权公开(公告)号：US09887705B2
公开(公告)日：2018-02-06
申请号：US15528164
申请日：2015-11-18
Applicant: NEC Corporation
Inventor： Masaaki Tanio , Shinichi Hori
IPC: H03M3/00 , H03M7/30 , H04B14/06 , H03L7/197 , G06F7/60 , H03F3/24 , H03M3/02 , H04L27/36 , H03L7/081
CPC classification number: H03M7/304 , G06F7/602 , H03F3/2171 , H03F3/24 , H03F3/245 , H03L7/0816 , H03L7/1976 , H03M3/02 , H03M3/37 , H03M3/502 , H03M7/3011 , H03M7/3015 , H04B14/062 , H04L27/36
Abstract: The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal.
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公开(公告)号：US20170047942A1
公开(公告)日：2017-02-16
申请号：US15307044
申请日：2015-01-28
Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Inventor： Takashi MAEHATA
IPC: H03M3/00
CPC classification number: H03M3/30 , H03M3/02 , H03M3/402 , H04B1/71637 , H04L1/0003 , H04L27/00
Abstract: Reduction in signal intensity of a harmonic component included in an output of a delta-sigma modulator is suppressed. A signal processing device includes: a delta-sigma modulator 11 that outputs a pulse signal; a first processor 12 that generates, from the pulse signal PO outputted from the delta-sigma modulator 11, a discontinuous pulse signal PC in which each of one-pulse sections in the pulse signal PO has a low level region on at least one of a rear end and a front end of the one-pulse section; and a second processor that generates a short-width pulse signal PS having a pulse width shorter than a pulse width of the discontinuous pulse signal PC generated by the first processor 12.
Abstract translation: 抑制包含在Δ-Σ调制器的输出中的谐波分量的信号强度的降低。 信号处理装置包括：Δ-Σ调制器11，其输出脉冲信号; 从Δ-Σ调制器11输出的脉冲信号PO生成不连续脉冲信号PC的第一处理器12，其中脉冲信号PO中的每一个脉冲区段中的至少一个具有低电平区域 后端和单脉冲部分的前端; 以及第二处理器，其生成具有比由第一处理器12产生的不连续脉冲信号PC的脉冲宽度短的脉冲宽度的短宽度脉冲信号PS。
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Patent Agency Ranking
公开(公告)号：US09312878B1
公开(公告)日：2016-04-12
申请号：US14522842
申请日：2014-10-24
Applicant: Hypres, Inc.
Inventor： Amol Inamdar , Deepnarayan Gupta
CPC classification number: H03M3/458 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/68 , H03M3/02 , H03M3/46
Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.
Abstract translation: 超导体模数转换器（ADC）具有高灵敏度和大动态范围。 进一步增加动态范围的一种方法是使用子架构，由此将粗略ADC的输出转换回模拟并从输入信号中减去，并将剩余信号馈送到精细ADC以产生额外的有效位。 这也需要高增益宽带线性放大器，这在超导体技术中通常不可用。 在优选实施例中，提出了分布式数字通量放大器，其还集成了积分，滤波和磁通减法的功能。 子阵列ADC设计提供了两个与物理放大器和减法器电路连接的ADC，可提供大约30-35 dB的动态范围扩展。
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公开(公告)号：US09252801B2
公开(公告)日：2016-02-02
申请号：US14231212
申请日：2014-03-31
Applicant: INTERSIL AMERICAS LLC
Inventor： Giri N K Rangan , Roger Levinson , John M. Caruso
Abstract: A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.
Abstract translation: Σ-Δ转换器可以包括耦合到第一求和电路和第二求和电路的滤波器。 多位量化器可以耦合到第二求和电路。 可以包括定义多位量化器和第一求和电路之间的反馈路径的单位数模转换器（DAC）。 可以包括限定第一求和电路和第二求和电路之间的前馈路径的前馈系数电路。
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公开(公告)号：US08988261B2
公开(公告)日：2015-03-24
申请号：US13884639
申请日：2011-10-20
Applicant: Roberto Lugli , Michael Korn , Alfred Zotz , Stephan Damith
Inventor： Roberto Lugli , Michael Korn , Alfred Zotz , Stephan Damith
CPC classification number: H03M3/02 , H03M3/358 , H03M3/506 , H03M7/3028
Abstract: A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges.
Abstract translation: Δ-ΣD / A转换器，数字值的输入信号可转换为二进制时钟信号时间离散的输出信号。 通过在多个时钟信号周期上形成输出信号的平均值，可以显示输入信号的模拟值。 Δ-ΣD / A转换器以这样的方式实现：在使用中，其通过串联布置一组信号模式的信号模式来提供输出信号，其中在每种情况下，该组信号模式， 二进制，时钟信号时间离散并在信号模式上延伸总共多个时钟周期。 该集合的至少两个信号模式具有相互不同的信号模式平均值，它们在相应的信号模式周期总数上形成，并且在每种情况下，该集合的所有信号模式具有基本上相同的数量，特别是完全相同的数量 ，边缘。
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公开(公告)号：US20140340250A1
公开(公告)日：2014-11-20
申请号：US14447315
申请日：2014-07-30
Applicant: PANASONIC CORPORATION
Inventor： Shiro DOSHO , Masao TAKAYAMA , Takuji MIKI
CPC classification number: G06G7/184 , H03H19/004 , H03K3/0315 , H03M3/02
Abstract: A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.
Abstract translation: 时间积分器集成了由两个信号之间的相位差表示的时间轴信息。 时间积分器包括：脉冲发生电路，被配置为将两个输入信号的边沿之间的时间差转换为两个脉冲信号的脉冲宽度之间的差，并输出两个脉冲信号，具有由两个脉冲变化的负载特性的负载电路 信号和耦合到负载电路的振荡电路，并且根据负载电路的负载特性使振荡频率发生变化。 作为时间积分的结果输出振荡电路的输出。
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公开(公告)号：US08717212B2
公开(公告)日：2014-05-06
申请号：US13623350
申请日：2012-09-20
Applicant: Phuong Huynh
Inventor： Phuong Huynh
IPC: H03M3/00
Abstract: An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.
Abstract translation: 提供了改进的正交带通采样Δ-Σ模数转换器，其包括环路滤波器，响应于环路滤波器的A / D和响应于A / D上变频的第一反馈D / A 频率乘第一乘法器和时钟。 第一求和电路响应于第一D / A和RF输入，用于向环路滤波器提供输入。 多个反馈D / AA响应于通过多个乘法器在不同频率中上变频的A / D和用于向环路滤波器提供反馈输入的多个时钟。 环路滤波器包括以级联配置布置的多个谐振器，多个模拟混频器，用于提供通过谐振器传播的误差信号的频移，以及响应于反馈D / A的多个求和电路。
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