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公开(公告)号：US12244322B2
公开(公告)日：2025-03-04
申请号：US17932572
申请日：2022-09-15
Applicant: QUALCOMM Incorporated
Inventor： Behnam Sedighi
Abstract: Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.
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12.发明授权公开(公告)号：US11705921B2
公开(公告)日：2023-07-18
申请号：US17337619
申请日：2021-06-03
Applicant: QUALCOMM Incorporated
Inventor： Xilin Liu , Nitz Saputra , Behnam Sedighi , Ashok Swaminathan , Dongwon Seo
Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.
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Patent Agency Ranking
13.发明授权公开(公告)号：US10797720B2
公开(公告)日：2020-10-06
申请号：US16367712
申请日：2019-03-28
Applicant: QUALCOMM Incorporated
Inventor： Eunyung Sung , Nitz Saputra , Behnam Sedighi , Ashok Swaminathan , Honghao Ji , Shahin Mehdizad Taleie , Dongwon Seo
Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.
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公开(公告)号：US10686476B1
公开(公告)日：2020-06-16
申请号：US16417455
申请日：2019-05-20
Applicant: QUALCOMM Incorporated
Inventor： Shahin Mehdizad Taleie , Nitz Saputra , Chen Jiang , Behnam Sedighi , Ibrahim Ramez Chamas , Bhushan Shanti Asuri , Dongwon Seo
Abstract: An RF-DAC transmitter is provided that includes an in-phase channel, a quadrature-phase channel, a first intermediate-phase channel, and a second intermediate-phase channel. Each channel includes a pair of interleaved RF-DACs for producing a pair of interleaved RF signals and a subtractor.
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公开(公告)号：US10666285B1
公开(公告)日：2020-05-26
申请号：US16202723
申请日：2018-11-28
Applicant: QUALCOMM Incorporated
Inventor： Shahin Mehdizad Taleie , Behnam Sedighi , Dongwon Seo , Parisa Mahmoudidaryan , Bhushan Shanti Asuri , Sang-June Park , Shrenik Patel
IPC: H03M1/66
Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.
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公开(公告)号：US10454509B2
公开(公告)日：2019-10-22
申请号：US15962865
申请日：2018-04-25
Applicant: QUALCOMM Incorporated
Inventor： Bhushan Shanti Asuri , Krishnaswamy Thiagarajan , Ashok Swaminathan , Shahin Mehdizad Taleie , Yen-Wei Chang , Vinod Panikkath , Sameer Vasantlal Vora , Ayush Mittal , Tonmoy Biswas , Sy-Chyuan Hwu , Zhilong Tang , Ibrahim Chamas , Ping Wing Lai , Behnam Sedighi , Dongwon Seo , Nitz Saputra
Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.
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公开(公告)号：US09819357B1
公开(公告)日：2017-11-14
申请号：US15593081
申请日：2017-05-11
Applicant: QUALCOMM Incorporated
Inventor： Wei Guo , Sang Min Lee , Behnam Sedighi , Dongwon Seo
Abstract: The present disclosure describes aspects of current removal for digital-to-analog converters (DACs). In some aspects, a circuit for converting a digital input to an analog output includes a first resistor ladder having first resistors connectable to respective current sources and connected to a first output of the circuit. The circuit also includes second resistor ladder having second resistors connectable to the respective current sources and connected to a second output of the circuit. A common node is formed between common resistor terminals of the first resistor ladder and the second resistor ladder. Current removal circuitry is connected to the common node and referenced to an amount of current provided by the respective current sources. By removing current from the common node of the resistor ladders, common-mode current at outputs of the circuit can be reduced with minimal degradation of differential performance of the circuit.
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