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    Delay-locked loop (DLL) with differential delay lines
    13.
    发明授权
    Delay-locked loop (DLL) with differential delay lines 有权

    公开(公告)号：US10447280B2

    公开(公告)日：2019-10-15

    申请号：US15711708

    申请日：2017-09-21

    Applicant: Qualcomm Incorporated

    Inventor： Ayush Mittal ,  Gajanan Maroti Devpuje ,  Bhushan Shanti Asuri ,  Krishnaswamy Thiagarajan

    IPC: H03L7/06 ,  H03L7/07 ,  H03L7/081 ,  H03K5/133 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

    Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.

    Floating Gate Switch
    15.
    发明申请
    Floating Gate Switch 审中-公开

    公开(公告)号：US20180062636A1

    公开(公告)日：2018-03-01

    申请号：US15634800

    申请日：2017-06-27

    Applicant: Qualcomm Incorporated

    Inventor： Hayg-Taniel Dabag ,  Bhushan Shanti Asuri ,  Hongyan Yan ,  Sy-Chyuan Hwu ,  Youngchang Yoon

    IPC: H03K17/16

    CPC classification number: H03K17/161 ,  H03K17/063 ,  H03K17/693 ,  H03K2217/0054 ,  H04B1/44

    Abstract: Various aspects of this disclosure describe configuring and operating a transistor switch. Examples include a self-biasing circuit that contains a diode-connected transistor whose source or drain is connected to the gate of a transistor configured as a switch. The diode-connected transistor is enabled and disabled responsive to voltage swings in the input signal to the transistor configured as a switch. When enabled, the diode-connected transistor may charge the floating gate voltage of the transistor configured as a switch. When disabled, the diode-connected transistor may acts as a high impedance to inhibit voltage discharge from the gate of the transistor configured as a switch.

    Configurable digital-analog phase locked loop
    16.
    发明授权
    Configurable digital-analog phase locked loop 有权
    可配置的数字 - 模拟锁相环

    公开(公告)号：US08884672B2

    公开(公告)日：2014-11-11

    申请号：US13705023

    申请日：2012-12-04

    Applicant: QUALCOMM Incorporated

    Inventor： Gary John Ballantyne ,  Jeremy D. Dunworth ,  Bhushan Shanti Asuri

    IPC: H03L7/00 ,  H03L7/085 ,  H03L7/089 ,  H03L7/093

    CPC classification number: H03L7/085 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093

    Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

    Abstract translation: 锁相环（PLL）器件可配置在模拟锁相环和混合模拟数字锁相环路中。 在模拟模式中，至少相位检测器，模拟环路滤波器和压控振荡器（VCO）被连接以形成模拟环路。 在数字模式下，连接至少相位检测器，压控振荡器（VCO），时间数字转换器（TDC），数字环路滤波器和数模转换器（DAC），以形成混合数字模拟 循环。

    CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP
    17.
    发明申请
    CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP 有权
    可配置数字模拟锁相环

    公开(公告)号：US20130181756A1

    公开(公告)日：2013-07-18

    申请号：US13705023

    申请日：2012-12-04

    Applicant: QUALCOMM Incorporated

    Inventor： Gary John Ballantyne ,  Jeremy D. Dunworth ,  Bhushan Shanti Asuri

    IPC: H03L7/085

    CPC classification number: H03L7/085 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093

    Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

    Abstract translation: 锁相环（PLL）器件可配置在模拟锁相环和混合模拟数字锁相环路中。 在模拟模式中，至少相位检测器，模拟环路滤波器和压控振荡器（VCO）被连接以形成模拟环路。 在数字模式下，连接至少相位检测器，压控振荡器（VCO），时间数字转换器（TDC），数字环路滤波器和数模转换器（DAC），以形成混合数字模拟 循环。

    Multi-band transmitter
    19.
    发明授权
    Multi-band transmitter 有权

    公开(公告)号：US11750253B2

    公开(公告)日：2023-09-05

    申请号：US17464404

    申请日：2021-09-01

    Applicant: QUALCOMM Incorporated

    Inventor： Chuan Wang ,  Bhushan Shanti Asuri ,  Li Liu ,  Vinod Panikkath

    IPC: H04B1/02 ,  H04B7/06 ,  H04B1/04

    CPC classification number: H04B7/0602 ,  H04B1/0483 ,  H04B2001/0491

    Abstract: In certain aspects, a method includes receiving a first intermediate frequency (IF) signal and a second IF signal via a common input, upconverting the first IF signal into a first radio frequency (RF) signal, transmitting the first RF signal via a first antenna array, upconverting the second IF signal into a second RF signal, and transmitting the second RF signal via a second antenna array. In a first transit mode, the first RF signal is in a first frequency band and the second RF signal is in a second frequency band, and, in a second transmit mode, the first RF signal and the second RF signal are both in the first frequency band.

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