公开(公告)号：US11670351B1

公开(公告)日：2023-06-06

申请号：US17456773

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Anil Chowdary Kota ,  Changho Jung ,  Chulmin Jung

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C7/106 ,  G11C5/14 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/12

Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

公开(公告)号：US11527282B2

公开(公告)日：2022-12-13

申请号：US17144077

申请日：2021-01-07

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Keejong Kim ,  Chulmin Jung ,  Ritu Chaba

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US11437091B2

公开(公告)日：2022-09-06

申请号：US17008476

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Percy Dadabhoy ,  Arun Babu Pallerla

IPC: G11C11/419

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. To assist the charge-transfer by the charge-transfer transistor, a first and second cross-coupled transistor are coupled between the bit line and a complement bit line.

公开(公告)号：US10923185B2

公开(公告)日：2021-02-16

申请号：US16431639

申请日：2019-06-04

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Keejong Kim ,  Chulmin Jung ,  Ritu Chaba

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C11/418 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US20150029782A1

公开(公告)日：2015-01-29

申请号：US13953473

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Rakesh Vattikonda ,  Nishith Desai ,  Sei Seung Yoon

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

Abstract translation: 包括一对交叉耦合的反相器的多端口位单元通过在写入操作期间从电源和接地中选择性隔离交叉耦合的反相器中的第一个而提供增加的写入速度和增强的工作电压范围。 写入操作通过写入端口发生，该写入端口包括被配置为将由第一交叉耦合的反相器驱动的第一节点耦合到写入位线的传输门极。 位单元中的剩余的第二交叉耦合反相器被配置为驱动耦合到多个读端口的第二节点。

公开(公告)号：US08830780B2

公开(公告)日：2014-09-09

申请号：US13741886

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Peng Jin ,  Sei Seung Yoon

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/148 ,  G11C8/10

Abstract: The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.

Abstract translation: 本公开涉及一种用于响应于一个或多个预解码地址线在对设备的至少一部分通电而被激活而停用存储器电路的一个或多个预解码地址线的装置。 具体地，该装置包括存储装置; 地址预解码器，被配置为基于输入地址激活多个预解码地址线中的一个或多个，其中所述多个预解码地址线耦合到所述存储器设备，用于访问与所述一个或多个激活的预解码的相关联的一个或多个存储器单元 地址线 以及上电复位电路，其被配置为响应于在对所述装置的所述至少一部分供电上启动的所述预解码地址线中的一个或多个来停用所述预解码地址线中的一个或多个。

公开(公告)号：US11763866B1

公开(公告)日：2023-09-19

申请号：US17702770

申请日：2022-03-23

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Anil Chowdary Kota ,  Changho Jung

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/08 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/12 ,  G11C8/08

Abstract: A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.

公开(公告)号：US11270762B1

公开(公告)日：2022-03-08

申请号：US17008433

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Arun Babu Pallerla ,  Percy Dadabhoy

IPC: G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C7/06 ,  H04M1/2745 ,  G11C11/412

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes the burst mode despite the presence of an intervening write operation to a row address not equal to the preceding row address.

公开(公告)号：US09858988B1

公开(公告)日：2018-01-02

申请号：US15206018

申请日：2016-07-08

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227 ,  G11C11/418

Abstract: A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.

公开(公告)号：US09646681B1

公开(公告)日：2017-05-09

申请号：US15137952

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Keejong Kim ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/4125 ,  H01L28/00

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a first circuit to store a bit and a second circuit to decouple the stored bit from a power supply and from a return. The method includes storing a bit in a memory cell by a first circuit and decoupling the stored bit from a power supply and a return by a second circuit. Another memory is provided. The memory includes a memory cell having means for storing a bit by a feedback and means for disabling the feedback.