公开(公告)号：US20140002205A1

公开(公告)日：2014-01-02

申请号：US13797356

申请日：2013-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： Abbas Komijani ,  Emmanouil Terrovitis ,  Justin A. Hwang

IPC: H03L7/00

CPC classification number: H03L7/103 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/087 ,  H03L7/10 ,  H03L7/113 ,  H03L7/181 ,  H03L2207/06

Abstract: A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

Abstract translation: 公开了一种频率合成器，其包括具有输出以输送可控频率的信号的振荡器。 振荡器包括响应于N位控制信号以显示电容的电容器组。 振荡器输出频率基于电容。 控制逻辑产生N位控制信号，并且通过二进制搜索步骤和N位控制信号的最低有效位（LSB）的调制来确定N位控制信号的每个位。 LSB调制与每个比特的二进制搜索相结合，导致更高的频率估计精度。

公开(公告)号：US09419662B2

公开(公告)日：2016-08-16

申请号：US14535928

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Brian James Kaczynski ,  Emmanouil Terrovitis

IPC: H04B1/06 ,  H04B7/00 ,  H04B1/10 ,  H03H7/25 ,  H03H11/24 ,  H04B1/16 ,  H04B5/00 ,  H01L29/92 ,  H04B1/18

CPC classification number: H04B1/109 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/92 ,  H01L29/94 ,  H01L2924/0002 ,  H03H7/25 ,  H03H11/245 ,  H04B1/16 ,  H04B1/18 ,  H04B5/0012 ,  H04B5/0025 ,  H01L2924/00

Abstract: A variable attenuator can be used with high-voltage radio-frequency signals. The attenuator can provide wide dynamic range with little loss at the lowest attenuation level. The attenuator may be implemented in digital integrated circuit processes and occupies small integrated circuit area. Additionally, the use of circuit elements external to the SoC may be reduced. The attenuator uses multiple attenuator cells connected in parallel to an RF input and RF output. The attenuator cells use capacitive dividers with pair of capacitors laid out in the same integrated circuit area. The capacitors are also laid out so that the RF input shields the RF output from ground to avoid parasitic capacitance on the RF output.

Abstract translation: 可变衰减器可用于高压射频信号。 衰减器可以提供宽动态范围，在最低衰减水平下几乎没有损耗。 衰减器可以在数字集成电路工艺中实现并且占用小的集成电路区域。 另外，可以减少SoC外部的电路元件的使用。 衰减器使用与RF输入和RF输出并联连接的多个衰减器单元。 衰减器单元使用具有一对电容器的电容分压器，布置在同一集成电路区域中。 电容器也布置成使得RF输入屏蔽来自地面的RF输出，以避免RF输出端的寄生电容。

公开(公告)号：US09048850B2

公开(公告)日：2015-06-02

申请号：US13797356

申请日：2013-03-12

Applicant: QUALCOMM Incorporated

Inventor： Abbas Komijani ,  Emmanouil Terrovitis ,  Justin A. Hwang

IPC: H03L7/10 ,  H03L7/087 ,  H03J5/24 ,  H03L7/113 ,  H03L7/181

CPC classification number: H03L7/103 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/087 ,  H03L7/10 ,  H03L7/113 ,  H03L7/181 ,  H03L2207/06

Abstract: A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

Abstract translation: 公开了一种频率合成器，其包括具有输出以输送可控频率的信号的振荡器。 振荡器包括响应于N位控制信号以显示电容的电容器组。 振荡器输出频率基于电容。 控制逻辑产生N位控制信号，并且通过二进制搜索步骤和N位控制信号的最低有效位（LSB）的调制来确定N位控制信号的每个位。 LSB调制与每个比特的二进制搜索相结合，导致更高的频率估计精度。

公开(公告)号：US08786329B1

公开(公告)日：2014-07-22

申请号：US13772039

申请日：2013-02-20

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03K3/017 ,  H03K5/156

CPC classification number: H03L7/0891 ,  H03K3/017 ,  H03K5/00006

Abstract: A clock multiplier circuit includes a clock generator, a delay element, a logic gate, and a duty cycle correction circuit. The clock generator generates a clock signal. The delay element generates a delayed clock signal in response to the clock signal. The logic gate generates a frequency-multiplied clock signal in response to the clock signal and the delayed clock signal. The duty cycle correction circuit generates an adjustment signal based at least in part on the frequency-multiplied clock signal. The clock generator adjusts a duty cycle of the clock signal in response to the adjustment signal.

Abstract translation: 时钟倍频电路包括时钟发生器，延迟元件，逻辑门和占空比校正电路。 时钟发生器产生时钟信号。 延迟元件响应于时钟信号产生延迟的时钟信号。 逻辑门响应于时钟信号和延迟的时钟信号产生倍频时钟信号。 占空比校正电路至少部分地基于倍频时钟信号产生调整信号。 时钟发生器响应于调整信号调整时钟信号的占空比。

公开(公告)号：US08723568B1

公开(公告)日：2014-05-13

申请号：US14137504

申请日：2013-12-20

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03L7/18

CPC classification number: H03L7/16 ,  H03K23/68 ,  H03L7/0812

Abstract: A clock generation circuit is disclosed that may generate a plurality of phase-delayed signals in a manner that may be relatively immune to VCO pulling. The clock generation circuit may include a circuit to generate an oscillating signal, a frequency divider to generate an RF signal having a frequency that is equal to 1/(n+0.5) times the frequency of the oscillating signal, wherein n is an integer value greater than or equal to one and n+0.5 is a non-integer value, and a DLL circuit to generate a plurality of local oscillator signals, wherein the local oscillator signals are phase-delayed with respect to each other.

Abstract translation: 公开了一种时钟产生电路，其可以以相对于VCO拉动相对的方式产生多个相位延迟的信号。 时钟发生电路可以包括用于产生振荡信号的电路，分频器，用于产生频率等于振荡信号频率的1 /（n + 0.5）倍的RF信号，其中n是整数值 大于或等于1且n + 0.5是非整数值，以及用于产生多个本地振荡器信号的DLL电路，其中本地振荡器信号相对于相位延迟。

公开(公告)号：US20140002152A1

公开(公告)日：2014-01-02

申请号：US13887888

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Emmanouil Terrovitis

IPC: H03L7/089

CPC classification number: H03L7/0893 ,  G11C7/222 ,  H03L7/099

Abstract: A charge pump circuit is disclosed that includes a main charge pump, a replica charge pump, and an op-amp. The main charge pump includes up and down input terminals to receive UP and DN control signals, a control terminal to receive a calibration signal, and an output to generate a control voltage. The replica charge pump includes up and down input terminals to receive DN and UP control signals, a control terminal to receive the calibration signal, and an output to generate a replica voltage. The op-amp generates the calibration signal in response to the control voltage and the replica voltage.

Abstract translation: 公开了一种电荷泵电路，其包括主电荷泵，复制电荷泵和运算放大器。 主电荷泵包括上下输入端子以接收UP和DN控制信号，控制端子接收校准信号，以及输出端产生控制电压。 复制电荷泵包括用于接收DN和UP控制信号的上下输入端子，用于接收校准信号的控制端子和用于产生复制电压的输出端。 运算放大器根据控制电压和复制电压产生校准信号。