公开(公告)号：US09941156B2

公开(公告)日：2018-04-10

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

公开(公告)号：US20160293475A1

公开(公告)日：2016-10-06

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Abstract translation: 公开了减小寄生电容的装置和方法。 器件可以包括电介质层。 该器件可以包括第一和第二导电结构以及靠近电介质层的蚀刻停止层。 蚀刻停止层可以限定靠近第一和第二导电结构之间的电介质层的区域的第一和第二开口。 该装置可以包括区域内的第一和第二气隙。 该装置可以包括靠近蚀刻停止层（例如，在上方，上方或上方）的材料层。 靠近蚀刻停止层的材料层可以覆盖第一和第二气隙。

公开(公告)号：US09252104B2

公开(公告)日：2016-02-02

申请号：US14512191

申请日：2014-10-10

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Bin Yang ,  Pr Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L29/00 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的下互连层。 CBC结构还包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上部互连层和第二上部互连层之间的金属绝缘体金属（MIM）电容器层。 此外，CBC结构还包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。

公开(公告)号：US20150091060A1

公开(公告)日：2015-04-02

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  PR Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间

公开(公告)号：US12218041B2

公开(公告)日：2025-02-04

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H01L49/02

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US11973019B2

公开(公告)日：2024-04-30

申请号：US17324614

申请日：2021-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L28/40 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16146

Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.

公开(公告)号：US20220344250A1

公开(公告)日：2022-10-27

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US20140203404A1

公开(公告)日：2014-07-24

申请号：US13745962

申请日：2013-01-21

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02

CPC classification number: H01L28/87 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.

Abstract translation: 公开了形成MoM电容器的螺旋金属金属（MoM或SMoM）电容器及相关系统和方法。 在一个实施例中，公开了一种设置在半导体管芯中的MoM电容器。 MoM电容器包括耦合到第一迹线的第一电极。 第一迹线卷绕在第一向内螺旋形的图案中并由第一平行迹线段组成。 MoM电容器还包括耦合到第二迹线的第二电极。 第二迹线卷绕在第一向内螺旋形图案中，并且包括间隔在第一平行迹线段之间的第二平行迹线段。 降低电容的变化允许电路设计者构建更严格公差的电路，并且通常提高电路的可靠性。

公开(公告)号：US20140197519A1

公开(公告)日：2014-07-17

申请号：US13743388

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/92

Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.

Abstract translation: 在特定实施例中，形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露其中将形成MIM电容器的区域。 绝缘层的第二部分形成在形成在该区域内的多个沟槽表面上的第一导电层上。 该方法还包括根据剥离技术去除绝缘层的至少第三部分。

公开(公告)号：US20130320494A1

公开(公告)日：2013-12-05

申请号：US13721089

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction.

Abstract translation: 一种具有多个金属层的半导体管芯，包括一组具有最小特征尺寸的优选方向的金属层。 金属层的组合使得相邻的金属层具有彼此正交的优选方向。 形成在金属层组中的手指电容器使得形成在一个金属层中的手指电容器具有平行于该金属层的优选方向的手指方向。 在双向金属层中，电容指可以在任一方向上。