公开(公告)号：US10194234B2

公开(公告)日：2019-01-29

申请号：US15613871

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jingxue Lu ,  Vijayakumar Dhanasekaran ,  Meysam Azin ,  Arash Mashayekhi ,  Kshitij Yadav

IPC: H04R1/10 ,  H03F3/183 ,  H04R1/06

Abstract: An example apparatus includes an output jack including a ground pole and a power output pole, a power supply circuit configured to generate a power signal, a coupler circuit operably coupled to the ground pole and the power output pole of the output jack, such that the coupler circuit is configured to couple the power signal with a noise signal on the ground pole to generate a combined output signal on the power output pole.

公开(公告)号：US20180069691A1

公开(公告)日：2018-03-08

申请号：US15255562

申请日：2016-09-02

Applicant: QUALCOMM INCORPORATED

Inventor： Matthew David Sienko ,  Meysam Azin ,  Weibo Hu

IPC: H04L7/00 ,  H04L25/06

CPC classification number: H04L7/0087 ,  H04L25/069 ,  H04L25/08

Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

公开(公告)号：US09658645B2

公开(公告)日：2017-05-23

申请号：US14713058

申请日：2015-05-15

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Meysam Azin ,  Alexander Khazin ,  Le Wang

IPC: G06F1/00 ,  G06F1/10 ,  G06F13/42 ,  G06F1/06

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F13/4291

Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

公开(公告)号：US20170054425A1

公开(公告)日：2017-02-23

申请号：US14982612

申请日：2015-12-29

Applicant: QUALCOMM Incorporated

Inventor： Srinidhi Koushik Kanagal Ramesh ,  Wenchang Huang ,  Meysam Azin

IPC: H03G3/30 ,  H03F3/185

CPC classification number: H03G3/3005 ,  H03F1/0272 ,  H03F1/48 ,  H03F3/185 ,  H03F3/3011 ,  H03F3/45475 ,  H03F3/45941 ,  H03F2200/03 ,  H03F2200/36 ,  H03F2203/30031 ,  H03F2203/45074 ,  H03F2203/45082 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45512 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45536 ,  H03F2203/45544 ,  H03G3/001 ,  H03G5/28

Abstract: Certain aspects of the present disclosure provide methods and apparatus for adjusting a bandwidth of an amplifier (e.g., a programmable gain amplifier (PGA)). In certain aspects, the PGA generally includes at least one amplification stage having an input and an output, a plurality of compensation capacitors, and at least one first switch configured to selectively couple at least one capacitor of the plurality of compensation capacitors between the input and the output of the at least one amplification stage. In certain aspects, the amplifier includes at least one second switch configured to selectively couple the at least one capacitor to a node such that the at least one capacitor is coupled to only one of the output or the node, where a voltage at the node is a differential mode (DM) reference potential for the amplification stage.

Abstract translation: 本公开的某些方面提供了用于调整放大器（例如，可编程增益放大器（PGA））的带宽的方法和装置。 在某些方面，PGA通常包括具有输入和输出的至少一个放大级，多个补偿电容器以及至少一个第一开关，其被配置为选择性地将多个补偿电容器中的至少一个电容器耦合在输入和 所述至少一个放大级的输出。 在某些方面，放大器包括至少一个第二开关，其被配置为选择性地将至少一个电容器耦合到节点，使得至少一个电容器仅耦合到输出或节点中的一个，其中节点处的电压为 用于放大级的差分模式（DM）参考电位。

公开(公告)号：US09391569B2

公开(公告)日：2016-07-12

申请号：US14230909

申请日：2014-03-31

Applicant: QUALCOMM Incorporated

Inventor： Meysam Azin ,  Arash Mehrabi ,  Wenchang Huang

IPC: H03F1/02 ,  H03F3/185 ,  H03F3/45 ,  H03F3/00 ,  H03F3/181 ,  H03F3/187 ,  H03H19/00 ,  H04R3/00

CPC classification number: H03F3/185 ,  H03F3/005 ,  H03F3/181 ,  H03F3/187 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/03 ,  H03F2203/45016 ,  H03F2203/45514 ,  H03H19/004 ,  H04R3/00

Abstract: An integrated DC blocking amplifier circuit, including: an operational amplifier configured in a differential amplifier; and at least first and second two-stage switched-capacitor circuits, each two stage switched-capacitor circuit including a first-stage circuit and a second-stage circuit, wherein the first two-stage switched capacitor circuit is connected to a positive side feedback path of the operational amplifier and the second two-stage switched capacitor circuit is connected to a negative side feedback path of the operational amplifier, wherein the first-stage circuit is switched at a relatively low switching frequency, while the second-stage circuit is switched at a relatively high switching frequency.

Abstract translation: 一种集成的DC阻塞放大器电路，包括：配置在差分放大器中的运算放大器; 以及至少第一和第二两级开关电容器电路，每个两级开关电容器电路包括第一级电路和第二级电路，其中所述第一两级开关电容器电路连接到正侧反馈 运算放大器和第二两级开关电容电路的路径连接到运算放大器的负侧反馈路径，其中第一级电路以相对低的开关频率切换，而第二级电路被切换 在相对高的开关频率。