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    Serial time-division-multiplexed bus with bidirectional synchronization/control word line
    1.
    发明授权
    Serial time-division-multiplexed bus with bidirectional synchronization/control word line 有权
    具有双向同步/控制字线的串行时分复用总线

    公开(公告)号：US09369272B2

    公开(公告)日：2016-06-14

    申请号：US14227235

    申请日：2014-03-27

    Applicant: QUALCOMM Incorporated

    Inventor： Zhilong Tang ,  Khosro Mohammad Rabii ,  Matthew David Sienko

    IPC: G06F1/12 ,  G06F13/42 ,  H04L7/04 ,  G06F11/10 ,  H04J3/06

    CPC classification number: H04L7/048 ,  G06F11/1004 ,  G06F13/4286 ,  G06F13/4295 ,  H04J3/0644 ,  H04J3/0652

    Abstract: One feature pertains to the synchronization of a serial time-division-multiplexed bus interconnecting an audio processing subsystem (i.e. a local node) with an audio coder-decoder (CODEC) subsystem (i.e. a remote node.) Control signals are transmitted along a bidirectional transmission line of the bus from the audio processing subsystem to the audio CODEC subsystem. The audio processing subsystem tracks an internal state machine phase count as the control signals are transmitted. The audio CODEC subsystem also tracks an internal state machine phase count as the signals are received. Transmission of control signals by the audio processing subsystem is periodically paused or suspended for a fixed interval of time based on the phase count to allow the audio CODEC subsystem to send a synchronization indicator signal back to the audio processing subsystem, which the audio processing subsystem uses to verify synchronization. This may be performed, for example, once every one hundred-twenty phase counts.

    Abstract translation: 一个特征涉及将音频处理子系统（即本地节点）与音频编码器 - 解码器（CODEC）子系统（即，远程节点）相互连接的串行时分多路复用总线的同步。控制信号沿双向传输 总线的传输线从音频处理子系统到音频CODEC子系统。 当发送控制信号时，音频处理子系统跟踪内部状态机相位计数。 随着信号被接收，音频CODEC子系统还跟踪内部状态机相位计数。 音频处理子系统的控制信号的传输基于相位计数周期性地暂停或暂停一段固定的时间间隔，以允许音频CODEC子系统将同步指示符信号发送回音频处理子系统使用的音频处理子系统 验证同步。 这可以例如每一百二十个相位计数执行一次。

    Differentiating-integrating sampling data receiver
    2.
    发明授权
    Differentiating-integrating sampling data receiver 有权

    公开(公告)号：US09979533B2

    公开(公告)日：2018-05-22

    申请号：US15255562

    申请日：2016-09-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： Matthew David Sienko ,  Meysam Azin ,  Weibo Hu

    IPC: H04L7/02 ,  H04L7/00 ,  H04L25/06

    CPC classification number: H04L7/0087 ,  H04L25/069 ,  H04L25/08

    Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

    Devices and methods for calibrating and operating a snapback clamp circuit
    3.
    发明授权
    Devices and methods for calibrating and operating a snapback clamp circuit 有权
    用于校准和操作快速恢复钳位电路的装置和方法

    公开(公告)号：US09182767B2

    公开(公告)日：2015-11-10

    申请号：US13794268

    申请日：2013-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Ankit Srivastava ,  Matthew David Sienko ,  Eugene Robert Worley

    IPC: H02H9/00 ,  G05F1/10 ,  H01L27/02 ,  H01L27/06 ,  H02H9/04 ,  H02H3/00

    CPC classification number: G05F1/10 ,  H01L27/0274 ,  H01L27/0277 ,  H01L27/0629 ,  H02H3/006 ,  H02H9/041 ,  H02H9/046

    Abstract: A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.

    Abstract translation: 一种设备包括一个快速恢复钳位电路，配置成响应于超过触发电压电平的电源电压来钳位电源电压。 在至少一个实施例中，快速恢复钳位电路包括钳位晶体管和可编程电阻部分，其响应于控制信号来校准触发电压电平。 或者或另外，快速恢复钳位电路可以包括可编程偏置装置，其被配置为通过偏置钳位晶体管的栅极端子来校准触发电压电平。 在另一个具体实施例中，公开了一种校准快速恢复钳位电路的方法。 在另一个具体实施例中，公开了一种操作集成电路的方法。

    CIRCUITS AND METHODS PROVIDING AMPLIFICATION WITH INPUT COMMON MODE VOLTAGE FOLLOWING
    4.
    发明申请
    CIRCUITS AND METHODS PROVIDING AMPLIFICATION WITH INPUT COMMON MODE VOLTAGE FOLLOWING 审中-公开
    具有输入公共模式电压放大的电路和方法以下

    公开(公告)号：US20170040952A1

    公开(公告)日：2017-02-09

    申请号：US14816622

    申请日：2015-08-03

    Applicant: QUALCOMM Incorporated

    Inventor： Zongyu Dong ,  Matthew David Sienko ,  Vijayakumar Dhanasekaran ,  Mayur Kantharaj Siddanna ,  Wenchang Huang

    IPC: H03F1/32 ,  H03F3/45

    CPC classification number: H03F1/3211 ,  H03F3/45 ,  H03F3/45237 ,  H03F3/45479 ,  H03F3/4565 ,  H03F2200/372 ,  H03F2203/45022 ,  H03F2203/45072 ,  H03F2203/45112

    Abstract: Methods, systems, and circuits for providing low-noise amplification with input common mode voltage following are disclosed. A circuit includes: an amplifier configured to receive a voltage input having an input common mode voltage and configured to generate a differential voltage output having an output common mode voltage; a feedback circuit in communication with the amplifier, the feedback circuit configured to receive the input common mode voltage and the differential voltage output and to generate a feedback voltage in response to the input common mode voltage and the differential voltage output; and an adjustable current source of the amplifier configured to receive the feedback voltage and to adjust a tail current of the amplifier in response to the feedback voltage.

    Abstract translation: 公开了用于提供具有输入共模电压跟随的低噪声放大的方法，系统和电路。 电路包括：放大器，被配置为接收具有输入共模电压的电压输入并被配置为产生具有输出共模电压的差分电压输出; 与所述放大器通信的反馈电路，所述反馈电路被配置为接收所述输入共模电压和所述差分电压输出，并且响应于所述输入共模电压和所述差分电压输出而产生反馈电压; 以及放大器的可调电流源，被配置为接收反馈电压并且响应于反馈电压来调节放大器的尾电流。

    DEVICES AND METHODS FOR CALIBRATING AND OPERATING A SNAPBACK CLAMP CIRCUIT
    5.
    发明申请
    DEVICES AND METHODS FOR CALIBRATING AND OPERATING A SNAPBACK CLAMP CIRCUIT 有权
    用于校准和操作反射夹钳电路的装置和方法

    公开(公告)号：US20140254051A1

    公开(公告)日：2014-09-11

    申请号：US13794268

    申请日：2013-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ankit Srivastava ,  Matthew David Sienko ,  Eugene Robert Worley

    IPC: H02H9/04 ,  G05F1/10

    CPC classification number: G05F1/10 ,  H01L27/0274 ,  H01L27/0277 ,  H01L27/0629 ,  H02H3/006 ,  H02H9/041 ,  H02H9/046

    Abstract: A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.

    Abstract translation: 一种设备包括一个快速恢复钳位电路，配置成响应于超过触发电压电平的电源电压来钳位电源电压。 在至少一个实施例中，快速恢复钳位电路包括钳位晶体管和可编程电阻部分，其响应于控制信号来校准触发电压电平。 或者或另外，快速恢复钳位电路可以包括可编程偏置装置，其被配置为通过偏置钳位晶体管的栅极端子来校准触发电压电平。 在另一个具体实施例中，公开了一种校准快速恢复钳位电路的方法。 在另一个具体实施例中，公开了一种操作集成电路的方法。

    DIFFERENTIATING-INTEGRATING SAMPLING DATA RECEIVER
    6.
    发明申请
    DIFFERENTIATING-INTEGRATING SAMPLING DATA RECEIVER 有权

    公开(公告)号：US20180069691A1

    公开(公告)日：2018-03-08

    申请号：US15255562

    申请日：2016-09-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： Matthew David Sienko ,  Meysam Azin ,  Weibo Hu

    IPC: H04L7/00 ,  H04L25/06

    CPC classification number: H04L7/0087 ,  H04L25/069 ,  H04L25/08

    Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

    SERIAL TIME-DIVISION-MULTIPLEXED BUS WITH BIDIRECTIONAL SYNCHRONIZATION/CONTROL WORD LINE
    8.
    发明申请
    SERIAL TIME-DIVISION-MULTIPLEXED BUS WITH BIDIRECTIONAL SYNCHRONIZATION/CONTROL WORD LINE 有权
    串行时分多路复用总线，具有双向同步/控制字线

    公开(公告)号：US20150280904A1

    公开(公告)日：2015-10-01

    申请号：US14227235

    申请日：2014-03-27

    Applicant: QUALCOMM Incorporated

    Inventor： Zhilong Tang ,  Khosro Mohammad Rabii ,  Matthew David Sienko

    IPC: H04L7/04 ,  G06F11/10

    CPC classification number: H04L7/048 ,  G06F11/1004 ,  G06F13/4286 ,  G06F13/4295 ,  H04J3/0644 ,  H04J3/0652

    Abstract: One feature pertains to the synchronization of a serial time-division-multiplexed bus interconnecting an audio processing subsystem (i.e. a local node) with an audio coder-decoder (CODEC) subsystem (i.e. a remote node.) Control signals are transmitted along a bidirectional transmission line of the bus from the audio processing subsystem to the audio CODEC subsystem. The audio processing subsystem tracks an internal state machine phase count as the control signals are transmitted. The audio CODEC subsystem also tracks an internal state machine phase count as the signals are received. Transmission of control signals by the audio processing subsystem is periodically paused or suspended for a fixed interval of time based on the phase count to allow the audio CODEC subsystem to send a synchronization indicator signal back to the audio processing subsystem, which the audio processing subsystem uses to verify synchronization. This may be performed, for example, once every one hundred-twenty phase counts.

    Abstract translation: 一个特征涉及将音频处理子系统（即，本地节点）与音频编码器 - 解码器（CODEC）子系统（即，远程节点）相互连接的串行时分多路复用总线的同步。控制信号沿双向传输 总线的传输线从音频处理子系统到音频CODEC子系统。 当发送控制信号时，音频处理子系统跟踪内部状态机相位计数。 随着信号被接收，音频CODEC子系统还跟踪内部状态机相位计数。 音频处理子系统的控制信号的传输基于相位计数周期性地暂停或暂停一段固定的时间间隔，以允许音频CODEC子系统将同步指示符信号发送回音频处理子系统使用的音频处理子系统 验证同步。 这可以例如每一百二十个相位计数执行一次。

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