公开(公告)号：US09123721B2

公开(公告)日：2015-09-01

申请号：US14132098

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L21/768 ,  H01L23/522 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US20150145143A1

公开(公告)日：2015-05-28

申请号：US14132098

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/522 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US11444068B2

公开(公告)日：2022-09-13

申请号：US16928939

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jonghae Kim ,  Periannan Chidambaram ,  Pratyush Kamal

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L21/762 ,  H01L21/48

Abstract: An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network.

公开(公告)号：US10121743B2

公开(公告)日：2018-11-06

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US10062680B2

公开(公告)日：2018-08-28

申请号：US14272981

申请日：2014-05-08

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H03K3/012 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/78696 ,  H03K3/012

Abstract: Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related systems and methods are also disclosed. In one aspect, a SOI CMOS standard library cell circuit is provided that is comprised of one or more standard library cells. Each standard library cell includes one or more PMOS channel regions and one or more NMOS channel regions. Each standard library cell has one or more gate back-bias rails disposed adjacent to PMOS and NMOS channel regions. The gate back-bias rails are configured to apply bias voltages to corresponding PMOS and NMOS channel regions to adjust threshold voltages of PMOS and NMOS transistors associated with the PMOS and NMOS channel regions, respectively. Voltage biasing can be controlled to adjust timing of an IC using SOI CMOS standard library cell circuits to achieve design timing targets without including timing closure elements that consume additional area.

公开(公告)号：US09754923B1

公开(公告)日：2017-09-05

申请号：US15149646

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du ,  Javid Jaffari

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  G06F17/50 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L25/16 ,  H01L27/0688 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434

Abstract: Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.

公开(公告)号：US09213358B2

公开(公告)日：2015-12-15

申请号：US14159028

申请日：2014-01-20

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: G06F17/50 ,  G06F1/10 ,  H01L27/06

CPC classification number: G06F1/10 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/62 ,  G06F2217/84 ,  H01L27/0688

Abstract: Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.

Abstract translation: 公开了单片三维（3D）集成电路（IC）（3DIC）跨层时钟偏移管理系统。 还公开了方法和相关组件。 在示例性实施例中，为了抵消可能在时钟树中的层次之间产生的偏斜，跨层时钟平衡方案​​利用自动延迟调整。 特别地，延迟感测电路检测不同层之间的时钟树中可比较点的延迟差异，并且指示可编程延迟元件在两个层级中更快地延迟时钟信号。 在第二示例性实施例中，金属网格被提供给时钟树中的所有元件，并且用作基本上同时向时钟元件提供时钟信号的信号聚合器。

公开(公告)号：US08836040B2

公开(公告)日：2014-09-16

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/118 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域的上方，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。

公开(公告)号：US20140246715A1

公开(公告)日：2014-09-04

申请号：US13784811

申请日：2013-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Pratyush Kamal ,  Mukul Gupta ,  Foua Vang

IPC: H01L27/07 ,  H01L21/8234

CPC classification number: H01L27/0811 ,  H01L27/016 ,  H01L29/66181 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract translation: 集成电路包括具有第一，第二和第三节点的电容器。 第一晶体管的第一和第二节点连接在一起，第二晶体管的第一和第二节点连接在一起。 第一晶体管的第三节点连接到第二晶体管的第三节点。 每个第三节点被构造成使得每个节点包括宽度和至少占宽度百分之十的长度。

公开(公告)号：US09929733B1

公开(公告)日：2018-03-27

申请号：US15437871

申请日：2017-02-21

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/522 ,  H03K19/094 ,  H01L23/528 ,  H01L27/06 ,  H01L27/118

CPC classification number: H03K19/094 ,  G06F17/505 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11872 ,  H01L2027/11875

Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.