公开(公告)号：US09053960B2

公开(公告)日：2015-06-09

申请号：US13784811

申请日：2013-03-04

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Mukul Gupta ,  Foua Vang

IPC: H01L27/07 ,  H01L27/08 ,  H01L29/66 ,  H01L27/01 ,  H01L29/94

CPC classification number: H01L27/0811 ,  H01L27/016 ,  H01L29/66181 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract translation: 集成电路包括具有第一，第二和第三节点的电容器。 第一晶体管的第一和第二节点连接在一起，第二晶体管的第一和第二节点连接在一起。 第一晶体管的第三节点连接到第二晶体管的第三节点。 每个第三节点被构造成使得每个节点包括宽度和至少占宽度百分之十的长度。

公开(公告)号：US10593700B2

公开(公告)日：2020-03-17

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L27/118 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US09887209B2

公开(公告)日：2018-02-06

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L21/44 ,  H01L27/118 ,  H01L23/535 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

公开(公告)号：US09640480B2

公开(公告)日：2017-05-02

申请号：US14723357

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon

IPC: H01L23/528 ,  H01L27/088 ,  G06F1/10 ,  G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L23/528 ,  G06F1/10 ,  G06F17/5068 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

公开(公告)号：US10965289B2

公开(公告)日：2021-03-30

申请号：US16267289

申请日：2019-02-04

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim ,  Mickael Malabry ,  Mukul Gupta

IPC: H03K19/0948 ,  H01L27/118 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/092

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US09831272B2

公开(公告)日：2017-11-28

申请号：US15264560

申请日：2016-09-13

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Satyanarayana Sahu ,  Hyeokjin Lim ,  Mukul Gupta

IPC: H01L27/118 ,  H01L29/06

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0649 ,  H01L2027/11829 ,  H01L2027/11866

Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

公开(公告)号：US20140246715A1

公开(公告)日：2014-09-04

申请号：US13784811

申请日：2013-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Pratyush Kamal ,  Mukul Gupta ,  Foua Vang

IPC: H01L27/07 ,  H01L21/8234

CPC classification number: H01L27/0811 ,  H01L27/016 ,  H01L29/66181 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract translation: 集成电路包括具有第一，第二和第三节点的电容器。 第一晶体管的第一和第二节点连接在一起，第二晶体管的第一和第二节点连接在一起。 第一晶体管的第三节点连接到第二晶体管的第三节点。 每个第三节点被构造成使得每个节点包括宽度和至少占宽度百分之十的长度。

公开(公告)号：US10175571B2

公开(公告)日：2019-01-08

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Hyeokjin Bruce Lim ,  Ohsang Kwon ,  Mickael Malabry ,  Jingwei Zhang ,  Raymond George Stephany ,  Haining Yang ,  Kern Rim ,  Stanley Seungchul Song ,  Mukul Gupta ,  Foua Vang

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

公开(公告)号：US09577639B1

公开(公告)日：2017-02-21

申请号：US14864486

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Bruce Lim ,  Mukul Gupta ,  Hananel Kang ,  Chih-lung Kao ,  Radhika Guttal

IPC: H03K19/0948 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528

CPC classification number: H03K19/0948 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924

Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.

Abstract translation: MOS器件包括具有第一MOS晶体管源极，第一MOS晶体管漏极和第一MOS晶体管栅极的第一MOS晶体管。 MOS器件还包括具有第二MOS晶体管源极，第二MOS晶体管漏极和第二MOS晶体管栅极的第二MOS晶体管。 第二MOS晶体管源和第一MOS晶体管源耦合到第一电压源。 MOS器件包括具有第三MOS晶体管栅极的第三MOS晶体管，第一MOS晶体管源极和第三MOS晶体管源极之间的第三MOS晶体管栅极，第三MOS晶体管还具有第三MOS晶体管源极和第三MOS晶体管漏极 所述第三MOS晶体管源耦合到所述第一MOS晶体管源，所述第三MOS晶体管漏极耦合到所述第二MOS晶体管源，所述第三MOS晶体管栅极浮置。

公开(公告)号：US11133803B2

公开(公告)日：2021-09-28

申请号：US15929520

申请日：2020-05-07

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim ,  Mickael Malabry ,  Mukul Gupta

IPC: H03K19/0948 ,  H01L27/118 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/092

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.