公开(公告)号：US09691462B2

公开(公告)日：2017-06-27

申请号：US14499153

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Taehui Na ,  Byungkyu Song ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C2207/002

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.

公开(公告)号：US09502091B1

公开(公告)日：2016-11-22

申请号：US14843546

申请日：2015-09-02

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Byung Kyu Song ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C11/16 ,  G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4097

Abstract: A sensing system may include a sense amplifier, a sensing circuit configured to sense a current difference, a data cell selectively coupled to the sensing circuit, a first reference cell selectively coupled to the sensing circuit, and a second reference cell selectively coupled to the sensing circuit. The resistance of the first reference cell and the second reference cell are different.

Abstract translation: 感测系统可以包括感测放大器，被配置为感测电流差的感测电路，选择性地耦合到感测电路的数据单元，选择性地耦合到感测电路的第一参考单元，以及选择性地耦合到感测的第二参考单元 电路。 第一参考单元和第二参考单元的电阻是不同的。

公开(公告)号：US09390779B2

公开(公告)日：2016-07-12

申请号：US13835251

申请日：2013-03-15

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Seung H. Kang ,  Jung Pill Kim

IPC: G06F11/22 ,  G06F17/50 ,  G11C11/16 ,  G11C13/00 ,  G11C27/02

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/002

Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.

Abstract translation: 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径检测数据信元的状态和参考信元的状态。 该方法还包括基于数据电压和参考电压确定数据单元的逻辑值。

公开(公告)号：US09165630B2

公开(公告)日：2015-10-20

申请号：US14015845

申请日：2013-08-30

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C11/16 ,  G11C7/06 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.

Abstract translation: 偏移消除双级感测方法包括：在第一级操作中使用由电阻性存储器参考单元的参考值产生的第一负载PMOS栅极电压来感测电阻性存储器数据单元的数据值。 该方法还包括使用在电阻性存储器感测电路的第二级操作中由电阻性存储器数据单元的数据值产生的第二负载PMOS栅极电压来感测电阻性存储器参考单元的参考值。 通过调整参考单元感测的工作点，与常规感测电路相比，偏移消除双级感测电路显着增加了感测余量。