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公开(公告)号：US11342961B1
公开(公告)日：2022-05-24
申请号：US17141025
申请日：2021-01-04
Applicant: QUALCOMM Incorporated
Inventor： Marvin Leroy Vis , Julio Zegarra , Thanh Duong , Thomas Funk , Erez Avigdor Falkenstein , Larry Flowers , Andrew Lejman , Joshua Britton , Tao Wang , Ali Morshedi
Abstract: Methods and apparatus are disclosed for near field radio-frequency (RF) testing of devices, particularly user equipment (UEs) capable of millimeter-wave (mmWave) transmissions. An exemplary test apparatus is described that uses a transducer to facilitate near field over-the-air testing of UEs in the mmWave transmission band. The transducer may be an orthomode transducer and may include a dual-polarity port positioned in the reactive near field of an antenna of a device under test (DUT). For UE signal transmission tests, the orthomode transducer splits test signals received from the antenna of the DUT via the dual-polarity port into a pair of single-polarity RF signals. The single-polarity RF signals are separately fed through a pair of waveguide-to-coaxial adaptors into separate coaxial cables, which feed coaxial transmission versions of the single-polarity RF signals to test equipment for analysis. UE signal reception tests are also described that utilize the same or different orthomode transducer.
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公开(公告)号：US10331526B2
公开(公告)日：2019-06-25
申请号：US15170742
申请日：2016-06-01
Applicant: QUALCOMM Incorporated
Inventor： Edwin Jose , Tao Wang
Abstract: Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.
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公开(公告)号：US09805495B2
公开(公告)日：2017-10-31
申请号：US15054717
申请日：2016-02-26
Applicant: QUALCOMM Incorporated
Inventor： Juraj Obert , Tao Wang , Vineet Goel
CPC classification number: G06T15/005 , G06T15/06 , G06T2200/28 , G06T2210/21
Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.
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公开(公告)号：US20170024926A1
公开(公告)日：2017-01-26
申请号：US14805088
申请日：2015-07-21
Applicant: QUALCOMM Incorporated
Inventor： Nagarjuna Duvvuru , Tao Wang , Jian Liang , Chunlin Wang
CPC classification number: G06T15/40 , G06T11/40 , G06T15/005 , G06T2200/04 , G06T2200/12 , G06T2200/28
Abstract: A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.
Abstract translation: 图形处理单元（GPU）可以包括被配置为确定三角形的坐标的三角形设置引擎（TSE），基于角度旋转三角形的坐标。 为了旋转坐标，TSE在旋转的域中生成三角形的坐标，并根据旋转域中的三角形的坐标确定旋转域中边界框的坐标。 TSE确定旋转域中的第一多个平行扫描线和旋转域中的第二多个并行扫描线。 第一和第二扫描线是垂直的。 TSE确定边界框坐标是否位于两个相邻的扫描线之内。 如果边界框坐标位于两个相邻的扫描线内，则TSE会从场景中删除三角形。
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公开(公告)号：US20150379663A1
公开(公告)日：2015-12-31
申请号：US14316275
申请日：2014-06-26
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Tao Wang , Chunhui Mei , Gang Zhong , Feng Ge
IPC: G06T1/20
CPC classification number: G06T1/20 , G06T11/40 , G06T15/005 , G09G5/363 , G09G2340/0407 , G09G2360/122
Abstract: In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.
Abstract translation: 在一个示例中，用于渲染图形数据的方法包括渲染多个箱的第一仓的像素，其中第一仓的像素与图像的第一部分相关联，并且向第一仓中呈现一个或 更多的像素位于图像的第一部分之外并且与多个箱的第二不同仓相关联。 该方法还包括将与第二仓相关联的一个或多个像素渲染到第二仓，使得一个或多个像素被渲染到第一仓和第二仓。
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Patent Agency Ranking
公开(公告)号：US20240078735A1
公开(公告)日：2024-03-07
申请号：US18067837
申请日：2022-12-19
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Andrew Evan Gruber , Tao Wang , Xuefeng Tang , Vishwanath Shashikant Nikam , Nigel Poole , Kalyan Kumar Bhiravabhatla , Fei Xu , Zilin Ying
IPC: G06T15/00
CPC classification number: G06T15/005
Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
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公开(公告)号：US11893654B2
公开(公告)日：2024-02-06
申请号：US17373704
申请日：2021-07-12
Applicant: QUALCOMM Incorporated
Inventor： Sreyas Kurumanghat , Kalyan Kumar Bhiravabhatla , Andrew Evan Gruber , Tao Wang , Baoguang Yang , Pavan Kumar Akkaraju
CPC classification number: G06T1/20 , G06T1/60 , G06T15/405
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a portion of a GPU to include at least one depth processing block, the at least one depth processing block being associated with at least one depth buffer. The apparatus may also identify one or more depth passes of each of a plurality of graphics workloads, the plurality of graphics workloads being associated with a plurality of frames. Further, the apparatus may process each of the one or more depth passes in the portion of the GPU including the at least one depth processing block, each of the one or more depth passes being processed by the at least one depth processing block, the one or more depth passes being associated with the at least one depth buffer.
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公开(公告)号：US20180189179A1
公开(公告)日：2018-07-05
申请号：US15423889
申请日：2017-02-03
Applicant: QUALCOMM Incorporated
IPC: G06F12/0811 , G06F12/0875 , G06F12/0846
CPC classification number: G06F12/0811 , G06F12/0846 , G06F12/0853 , G06F12/0875 , G06F2212/1016 , G06F2212/455
Abstract: A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.
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公开(公告)号：US20170352182A1
公开(公告)日：2017-12-07
申请号：US15174110
申请日：2016-06-06
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Xuefeng Tang , Jian Liang
CPC classification number: G06T15/30 , G06T1/20 , G06T15/005 , G06T15/40 , G06T15/405
Abstract: A graphics processing unit (GPU) may perform a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene, including performing low-resolution z-culling of representations of the plurality of primitives based at least in part on a first set of culling z-values each having a first test size to determine a first set of visible primitives from the plurality of primitives. The GPU may further perform a rendering pass to render the plurality of tiles based at least in part on performing the low-resolution z-culling of representations of the first set of visible primitives based at least in part on a second set of culling z-values that represents a second test size to determine a second set of visible primitives from the first set of visible primitives, wherein the first test size is greater than the second test size.
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20.发明授权公开(公告)号：US09626762B2
公开(公告)日：2017-04-18
申请号：US14686696
申请日：2015-04-14
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Tao Wang , Young In Yeo , Vineet Goel
CPC classification number: G06T7/70 , G06T1/20 , G06T1/60 , G06T13/80 , G06T15/005 , G06T15/80 , G06T2210/12
Abstract: Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.
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